[beginner] Using design symmetries ?

[Altera_Forum]

Hi everyone. 

 I'm currently building a signal processing circuit written in Verilog, which consists in a matrix of identical modules, with a few wires for inter-module communication.   Most signals go from one module to one of its immediate neighbours. Only the clock, clock_enable ans reset signals fan out to every module.   Is there a way to make Quartus aware of this "grid symmetry" to help it speed up the fitting/timing process ? Currently the verilog code just consists in writing N*N instantiations of my base module, and compilation time increases well beyond what I expected when I increase the size N of the matrix.   Thanks.

[Altera_Forum]

You can use bottom-up incremental compilation. See the incremental compilation chapter in the Quartus handbook for details. 

 You would compile the replicated block once, export the compilation results for that block, and import into the Quartus project containing the multiple instantiations of that block. This will work well for synthesis. This will also work to preserve placement (but not routing) if you can place all the instances such that the relative placement within each instance is identical. This requires that the sequence of RAM block, DSP block, and LAB columns overlapped by the replicated circuit be identical for all instances.  For other ways to reduce compilation time, see "Tools --> Advisors --> Compilation Time Advisor". There is an optimization chapter in the Quartus handbook that might have more suggestions than this Advisor covers.