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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16597 Discussions

DDR Sdram

Altera_Forum
Honored Contributor II
‎07-16-2008 03:52 PM
1,101 Views

Hi everyone, 

i want to implement a simple system with a Nios and a ddr sdram controller on a stratix ii development board. I have created it with sopc builder but when i try to compile it i always receive, during Timing Analyzer, the error  

"Error: Couldn't find the clock output pins. Stop. 

Error: 0 DQ pins found for variation 'ddr_sdram_0' but it was configured to be 16 bits wide. 

Error: Can't find hierarchy path. 

Error: The hierarchy path could not be found, possibly due to previous errors" 

Can anyone help me? 

Thank you!
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Altera_Forum
Honored Contributor II
‎07-16-2008 05:45 PM
397 Views

Search www.altera.com for "Couldn't find the clock output pins. Stop" including the quotes. You will get one search hit, which will take you to MegaCore release notes that have a suggestion for that error.

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Altera_Forum
Honored Contributor II
‎07-21-2008 07:57 AM
397 Views

ok, thank you! 

I'll try!
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Altera_Forum
Honored Contributor II
‎07-21-2008 12:18 PM
397 Views

I followed the suggestion found in altera document "megacore ip library, release note and errata" but i couldn't solve my problem. 

Any idea? 

I'm using Quartus 7.2
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Altera_Forum
Honored Contributor II
‎07-25-2008 05:48 PM
397 Views

Have you added the .sdc files to to the timequest analyzer?

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