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LVDS test with Boundary Scan

Altera_Forum
Honored Contributor II
‎07-22-2008 09:40 AM
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I am having an ADC with LVDS outputs , the lvds outputs are conected to a Stratix III. 

I want to test the Stratix LVDS inputs with Boundary scan .My plan was to use a DAC (or R2R) connecting to the ADC . 

It's no problem to create patterns for the DAC, but I am having some problems (i think) to detect de LVDS levels on the fpga site. 

 

Using MorphIO ? ( I do not have experience with this)  

Or configure the Stratix with a TAP controller and LVDS Rx to a "single normal" level / boundary scan cell ? 

Does anyone has an idea ? 

Thanks , Hans
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Altera_Forum
Honored Contributor II
‎07-23-2008 02:48 AM
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Stratix III does not support LVDS boundary scan. Only the P pin can accept the signal while the N pin is ignored. You can use BSDLCustomizer from Altera to modify the BSDL file to test for LVDS pins.

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