Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20644 Discussions

Help: HSMC and I2C

Altera_Forum
Honored Contributor II
1,367 Views

I am having a hell of a time trying to interface a camera through an HSMC - Santa Cruz adapter board (THDB-H2S - http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=39&no=219

 

On a typical HSMC connector, are the I2C pins electrically different than PIO pins? If so this would indicate that my problem has been a failure in sending I2C reliably through PIO pins.  

 

If not, could the level shifter on this adapter be causing my problems? 

 

The THDB-H2S uses the regular HSMC I2C pins for accessing EEPROM storage on the adapter. 

 

Any help with this would be greatly appreciated.
0 Kudos
17 Replies
Altera_Forum
Honored Contributor II
615 Views

I also got problem when I configing the I2C device through the HSMC connector.

0 Kudos
Altera_Forum
Honored Contributor II
615 Views

I am still having problems with this. Anyone?

0 Kudos
Altera_Forum
Honored Contributor II
615 Views

Now I'am sure the key is not about the HSMC, I interfaced an I2C component through an HSMC successfully. Did you use pull-up resistance on the SDA and SCL on the board? And you can try to define the SDA and scl pins as "weak pull up resistor " in the assignment edit. 

Wish this help
0 Kudos
Altera_Forum
Honored Contributor II
615 Views

With weak pull-up, SDA and SCL rise time may be too slow. You can slow down the I2C master timing in this case or use external strong pull-ups. They should me connected to 3.3V VCC to achieve a higher level without level translation. SCL could also use a push-pull driver, if no clock stretching is implemented by the slave. (Most likely it is neither used by the slave nor supported by the master).

0 Kudos
Altera_Forum
Honored Contributor II
615 Views

 

--- Quote Start ---  

SCL could also use a push-pull driver, if no clock stretching is implemented by the slave. (Most likely it is neither used by the slave nor supported by the master). 

--- Quote End ---  

 

 

I would definitely try using push-pull for the I2C clock.
0 Kudos
Altera_Forum
Honored Contributor II
615 Views

I've recently resurrected this project after taking a needed break. Unfortunately my situation is similar. 

 

I've been able to view the clock and data signals using a logic analyzer and their appears to be interference on the lines. For example, the data line will blip low at random intervals. This translates into incorrect bits being received on either end. 

 

Could this be a problem with the pull up resistor not being large enough? Anyone had similar problems? 

 

Thanks
0 Kudos
Altera_Forum
Honored Contributor II
615 Views

See a screenshot of the i2c in action below. I am writing on SCL_CAM and SDA_CAM. 

As you can see there is a lot of mess. 

 

http://img222.imageshack.us/img222/6883/tempar1.png
0 Kudos
Altera_Forum
Honored Contributor II
615 Views

You didn't tell about the used pull-up value. How can we determine, if it's appropriate? Furthermore, it has been said, that SCL can be driven by a push-pull output in most cases. Exactly, if only one I2C master exists (obviously) and the slave doesn't uitilize clock stretching (very likely, but you can check in the datasheet).

0 Kudos
Altera_Forum
Honored Contributor II
615 Views

Tell us also if you have used capacitors on the two SCL_CAM and SDA_CAM lines, and if yes, which values you used. Also be careful about the current drive strength on the two FPGA pins, it could be too high. Try to reduce the drive strength to lower values.

0 Kudos
Altera_Forum
Honored Contributor II
615 Views

 

--- Quote Start ---  

You didn't tell about the used pull-up value. How can we determine, if it's appropriate? Furthermore, it has been said, that SCL can be driven by a push-pull output in most cases. Exactly, if only one I2C master exists (obviously) and the slave doesn't uitilize clock stretching (very likely, but you can check in the datasheet). 

--- Quote End ---  

 

 

Honestly, I am not that experienced with i2c or fpga's in general so please bare with my ignorance as I work through this. 

 

I am not using any external resistors (I don't even see how I could). The pull up value is whatever the "Weak pull up resistor" refers to in the Quartus II Assignment editor. How would I utilize push-pull? 

 

 

--- Quote Start ---  

Tell us also if you have used capacitors on the two SCL_CAM and SDA_CAM lines, and if yes, which values you used. Also be careful about the current drive strength on the two FPGA pins, it could be too high. Try to reduce the drive strength to lower values. 

--- Quote End ---  

 

 

The lines include a level conversion from 2.5 to 3.3 V (hsmc - santa cruz adapter - see my earlier post) which may introduce stray capacitance onto the line. Unfortunately there is no detailed schematic for the Terasic converter. 

 

How would I go about reducing the drive strength?
0 Kudos
Altera_Forum
Honored Contributor II
615 Views

Are there any parameters or tricks one can use to "tweak" the pull up values that Quartus II implements on the Cyclone fpga's? 

 

Or if not, what would be the best way to implement i2c using my own resistors?  

I am using an EP3C120F780C7 in a video development kit
0 Kudos
Altera_Forum
Honored Contributor II
615 Views

Weak pull-ups are definitely too weak for regular I2C speed at some load capacitance. They can't be set to a higher strength. You should use external resistors of 1K to 4.7K maximum. As said, for SCL a push-pull driver can be used instead for most I2C applications, so basically an approriate SDA pull-up is what you need urgently.

0 Kudos
Altera_Forum
Honored Contributor II
615 Views

Ah I see. 

I am a little cloudy on how I would go about using an external pull up. I suppose I would connect a 3.3V source behind a 1k-4.7k resistor connected to the i2c data line. But can I connect this anywhere along the signal path?  

 

Another idea: 

What if I turned off pci coupling and interfaced the boards as 3.3v - 3.3v? Might this reduce capacitance from level shifting and help the internal weak pull up to work?
0 Kudos
Altera_Forum
Honored Contributor II
615 Views

What I mean by where do I connect the pull up resistor is that the daughter board interfaces with an hsmc port and from there I am not able to access any pins along the i2c line. 

I've noticed an option to define a pin as an external input... but how would I connect anything external to it? The only accessibly pins on this board are the hsmc ports or external clock. 

 

Anyone?
0 Kudos
Altera_Forum
Honored Contributor II
615 Views

I don't have schematics or other documentation of the said daughter board. Technical, you can place the pull-up anywhere at the I2C bus. This results from the fact, that the resistor value is high compared to trace impedances. 

 

I guess, there should be a place, where you can solder an SMD chip or leaded resistor. I also don't know, why the board designers didn't think about this issue. But there's definitely no software method to replace a regular I2C pull-up, except for considerably slowing down the transmission speed, as said.
0 Kudos
Altera_Forum
Honored Contributor II
615 Views

I'm not sure how I missed this, but the camera I am interfacing with does have 1k resistors pulling up the sda and scl lines to 3.3 V. 

 

I am having some success reading from the camera if I slow it down far enough, but not consistently. Writing to the board never seems to work though. I looked into the schematic of some generic i2c level shifters online, and they seem to use a pull up resistor on either side of the conversion. Ie, up to 2.5 on the fpga side, and up to 3.3 on the slave. It seems that now I have to figure out how to get an external resistor hooked up to the fpga side. Unfortunately this seems impossible...
0 Kudos
Altera_Forum
Honored Contributor II
615 Views

Without knowing the level shifter details, I can't say. There are different devices in use for this pupose. I don't even know the I2C voltage level at the camera module.

0 Kudos
Reply