Connecting unused pins

[Altera_Forum]

Hello everyone, 

 I have a design using a Cyclone III, with some unused pins. I wonder what would be the best recommendation about what to do with these pins. By default Quartus reserve these pins as input with weak pull-up, which means that they can be left unconnected. I've seen other recommendations telling to connect them to ground to reduce ground bounce, or even to connect some to ground and some to VCCIO, to reduce both ground bounce and VCC sag (AN224, AN466). In Quartus I can assign the unused pins to "output driving ground" or "input with weak pull-up", but not as "output driving VCCIO". I assume that using "input with weak pull-up" and connecting externally the pins to VCC won't be very efficient against VCC sag due to the pull-up impedance. So what would be the recommendation? - define all unused pins as "output driving ground" and connect them to ground externally - define some as "output driving ground" and some as "input with weak pull-up" and connect them externally to ground/VCCIO - define some as "output driving ground" and the other as regular I/O, force them to the value '1' in the design, and connect the pins externally to ground/VCCIO  I don't have any differential or reference voltage I/O on my design, but I have parallel busses with LVTTL 1.8 and 2.5V, with frequencies between 50 and 100MHz.  Thank you for your advice!

[Altera_Forum]

I guess those pins should be input tri-stated!

[Altera_Forum]

Generally I set unused pins to"output driving ground".  

 Be totally sure that the unused pins are not connected to VCC or external logic on your PCB!  Ground bounce reduction is always a good thing and the extra "GND" pins can help with noise imunity when routing.  Setting unsued pins to "input tri-stated" ensures that you will not have contention with external devices so can be of use.  Personally, I wouldn't go down the route of drivings logic '1' from your device and using pull-ups to VCC.

[Altera_Forum]

I don't know why I didn't notice it at first but there is also the option "reserve as input tri-stated with bus-hold circuitry". In that case the logic level on the unused pin is sampled at the end of configuration, and maintained during user mode. I could use this mode and connect half the unused pins to ground, and the other half to vccio, couldn't I? 

Or is it better to stick everything to ground and don't really care about vcc sag?  Thank you!

[Altera_Forum]

Driving unused pins to GND (or VCCIO) requires definition of all connected hardware pins in the top design, even if they are yet unused. This is a serious disadvantage to my opinion. Thus weak pull-up (or bus-hold) is the best selection for most designs. Interestingly, the Quartus default has been changed to weak pull-up with newer devices (most likely to avoid I/O driver damage with shorted pins).

[Altera_Forum]

--- Quote Start ---  I don't know why I didn't notice it at first but there is also the option "reserve as input tri-stated with bus-hold circuitry". In that case the logic level on the unused pin is sampled at the end of configuration, and maintained during user mode. I could use this mode and connect half the unused pins to ground, and the other half to vccio, couldn't I? Or is it better to stick everything to ground and don't really care about vcc sag?  --- Quote End ---    Bus hold is useful to prevent the FPGA input buffer from floating when the pin is not driven at all external to the FPGA. However, I think it has no advantage for you over "As input tri-stated" if you are going to connect the pin externally to GND or VCC.      --- Quote Start ---  Driving unused pins to GND (or VCCIO) requires definition of all connected hardware pins in the top design, even if they are yet unused.  --- Quote End ---    Setting "Reserve Pin" to "As output driving ground" for individual pins in the Assignment Editor or Pin Planner or for all unused pins in the Device and Pin Options dialog box is an alternative to having the pins in the top-level design entity. This is a way to reserve pins that are not in the design files at all. The .pin file will label these pins as "GND*", for which the .pin file says, "For non-transceiver I/O banks, connect each pin marked GND* directly to GND or leave it unconnected."

[Altera_Forum]

For years, the default for unused pins was "As output driving ground", which was a bad choice for obvious reasons. Starting with Stratix III and Cyclone III, the default is "As input tri-stated with weak pull-up". 

 I almost killed a few development boards by starting a new project and forgetting to change the default. In fact, I suspect there are a few seldom-used peripherals that died a horrible electrically conflicted death at some point in the last few years.

[Altera_Forum]

I disliked the old project-wide default because of the issue HDL Guru described. I urge being very careful if using "As output driving ground" in the Device and Pin Options dialog box. If intentionally having the FPGA drive unused pins to GND, I recommend using this setting on the individual pins through a "Reserve Pin" assignment in the Assignment Editor or Pin Planner. By manually adding this assignment pin by pin (even if you think you want it on every unused pin), you are less likely to overlook a pin that is driven to something other than GND on the board and that therefore needs a different setting. 

 While less dangerous, a project-wide default of "As input tri-stated" can cause trouble by leaving FPGA input buffers floating on pins that are not driven or pulled up on the board. Floating inputs can increase power, increase switching noise, and decrease device reliability. The project wide defaults using pull ups or bus hold are safer because they are more tolerant of a mistake where the user overlooks an unused pin that is driven on the board.

[Altera_Forum]

Thank you all for your answers! I think I'll use tri-stated inputs or bus hold and externally connect the pins to ground or vcc.