Driving PLL problem

[Altera_Forum]

Hello, 

 I am actually experiencing problems while trying to compile a design with PLL. I get a error telling that the PLL must be driven by a non-inverted input pin bla bla...  The input of my PLL is connected to the output of a multiplexer which has two clock in input ( directly link to CLK pins in the StratixII device ). Why does it not recognise the input of the PLL has being as a derived clock?  ( I tried to put it in the list of clock in the timing analyser seetings, but nothiing to do... )  Could you help me there?  Regards

[Altera_Forum]

Are you getting a fitting error(i.e. it won't fit)? What device? Making a change to the timing requirements won't change whether it fits. 

If you're muxing two clocks, you should try to use the built-in clock mux on the PLL(depending on the device). Open the megafunction again and try to use the built-in hardware.

[Altera_Forum]

Well, Compiler already crashes in the Analysis & Synthesis stage. 

I am using the EP2S180F1508C3. I have followed your recommendation, and used the megafunction ALTCLKCTLR. So I have directly 4 clk input for my block, all 4 linked to clock input pins (CLK1n, CLK1p, CLK9n, CLK9p ). I still have an error in t he analysis stage where it complains that my two last input must be driven by a PLL clock ouput...   What am I supposed to do?? there just simple clock inputs...   Thanks for your help.

[Altera_Forum]

In the Stratix III Handbook, look up the "Stratix III Global Clock Control Block". This shows the mux for getting onto the global. As you can see, the dynamic clock selelct chooses between two dedicated clock inputs(CLKp pins) and 2 PLL outputs(PLL Counter Outputs). The other mux in the diagram is static, i.e. it's chosen during configuraiton. So it looks like you're trying to drive it with four dedicated clock pins, which won't work. 

 So it sounds like you have four dedicated clock inputs you're muxing between, and were originally doing this in logic(which worked), but then drove this into a PLL(which didn't). Why were you trying to drive this into a PLL? (The first thing a PLL does is clock tree compensation, but once you've done general logic clock muxing, this advantage doesn't make sense. But you might be trying to use the PLL for something else, like to make different clock frequencies or do phase shifts.)  Anyway, I would suggest either: - Muxing the four clocks in logic and not using a PLL(and knowing what you're doing, i.e. glitch control, timing analysis, cross-clock analysis, etc.) - Having all four clocks go through individual PLLs and then mux them in logic - Don't mux your clocks(may not be an option) and design around what you're trying to do, i.e. have a master clock domain and then the data streams coming in on other domains connect to the master through asynch FIFOs.

[Altera_Forum]

Yes.I also met this problem.But that's so wierd,isn't? THe altclkctrl is just a mux.Why can't we input 4 clock signals all from the same PLL?:mad:

[Altera_Forum]

Many of the select bits are configuration bits and can't be modified dynamically. Annoying.

[Altera_Forum]

--- Quote Start ---  Many of the select bits are configuration bits and can't be modified dynamically. Annoying.  --- Quote End ---     So now rather than using the clk megafunction, I am trying to just use a mutiplexier to select the different clocks generated by the PLL and feed the output to the CPU's clock. I am now trying to see whether it works

[Altera_Forum]

Do not do a generic 4:1 mux in logic. That could get synthesized in a way that makes glitches. Build a 2:1 mux and keep attribute on the output signal/wire.(Open the HDL file in Quartus and go to Edit -> Insert Template -> VHDL or Verilog -> Synthesis Attributes for details on keep. This means the clock will only feed one LUT at a time. Synthesis has an uncanny way of making your 4:1 mux smaller/faster, which is good for general logic, but too often results in the clock feeding two LUTs at once, and results in glitches.

[Altera_Forum]

--- Quote Start ---  Do not do a generic 4:1 mux in logic. That could get synthesized in a way that makes glitches. Build a 2:1 mux and keep attribute on the output signal/wire.(Open the HDL file in Quartus and go to Edit -> Insert Template -> VHDL or Verilog -> Synthesis Attributes for details on keep. This means the clock will only feed one LUT at a time. Synthesis has an uncanny way of making your 4:1 mux smaller/faster, which is good for general logic, but too often results in the clock feeding two LUTs at once, and results in glitches.  --- Quote End ---     Hi,Thank you very much for your suggestion!  Actually your suggestion is very important to me ! Now what I am going to do is to create several clock signals using PLL and feed them to the CPU clock(this is because I need to change the CPU frequency dynamically during runtime for research purpose) . I use fixed clock for other components in SOPC(such as SDRAM) and then I use clock bridge to connect them to the CPU. I am trying to use PIO to control the multiplexier during the runtime to change the CPU clock input. So your suggestion is that if I want to use 4 clocks ,I 'd better use 3 2-input mutiplexier rather than 1 4-input mutiplexier and change some thing in the systhesis option as you told me ( actually I am not quite understand your words about how to change the option but I will try).   Thanks very muck!

[Altera_Forum]

I have searched the forum and found this thread 

http://www.alteraforum.com/forum/showthread.php?t=2388 I think it is very helpful for such problem