output timing improvement

[Altera_Forum]

Dear team,  

I am beginner to Quartus tool. I am in design phase and deciding on latency values using mega wizard arithematic components.   I am using STARTIXII device with Quartus II tool. The device is EP2S130F1508C3. Timing Quest is used for analysis. My timing requirement is 300mhz clock.    I implemented adder13 using megawizrd . Used SDC for basic constraints like clock,IO delay and clock uncertainty. Since this design is bottom module in my top level, i set virtual pin settings for my Output ports. I implemented the timing optimization advisors also. Always my setup paths are (From Register to Output port ) is violating.    The reason for Reg to Output port violation is, clock network delay. At launching path, the clock network delay 3.5ns and at capturing path (Latch path) clock network delay is 0ns. My clock period is 3.3 ns, is not sufficient for my clock network delay it self.   My concerns are , 1) how can i reduce clock network delay in this case?.   2) Since its bottom module, can i ignore the Reg to output port paths.  3) I tried applying IO delays wrto Virtual clocks and tried to set false path from reg clock to Virtual clock (AM i correct in this case?).   Please suggest me , How can i improve my timing?. I need max frequency is around 300mhz. Can we achieve 300mhz with StartixII devices or not?. Suggest Fitter settings for improving max freq?.   Is there any document regarding SDF generation in Quartus II tool. To decide on latency values, I am doing Gate level simulations with modelsim. I am curious to know, how these values is calculated by tool?.   Can any one suggest me , how can i find the latency value without doing GLS?.   Regards,  Sam

[Altera_Forum]

I/O timing is a completely different beast then internal timing, and will not easily run at 300MHz(you will most likely have to do source synchronous, where the clock and data are routed together.) But since this is not the real I/O in your design, just ignore it. Don't add a set_output_delay constraint to something that isn't going to be a real I/O. 

 (And if you do want to improve the clock network delay, use a PLL. THe delay is still there, but the PLL creates a clock that compensates(or basically shifts back in time) the clock it is sending. But again, don't do I/O constraints if it's not a real I/O)  And yes, it can do 300MHz, but it is by no means trivial to do.