All stx 2 running on single clk pin(no ppm offset)

[Altera_Forum]

Hi  

Im new to altera FPGAs.  I went throughout Stx II handbook but one thing is still not clear to me whether is possible.    Can I run the entire device based on one fast PLL which I only need to double the frequency?    For instance I was planning to use Fast PLL4 fed by dedicated clkp/n 11 input pins. Then driving one the global clocks GCLK 9-11 and use it to spread the clock to all banks and also to use it as reference clk to enhanced PLL5 and 6. It says only dedicated global clocks can be used as reference of PLL5,6.  I was planning to use the PLL5,6 outputs as clocks for which some phase programmability is possible vs. their input clock.    Thanks,

[Altera_Forum]

I haven't tried it, but for the internal of the device it is possible, for reference to other PLL's, it's "Maybe" possible. 

 Not all Altera families allow input to the PLL's to come from internal global clocks. And all will usually give you a "Jitter" performance warning when doing this.  What I would do, is lock down the PLL locations you want to use and at the start of the design, hook up at least the PLL's and external clocks and build it to make sure everything works, and you are "OK" with any warning's given.  Pete

[Altera_Forum]

I do NOT think you can (should) do this. 

 Check the jitter spec's omn the PLL's you are looking to use. The cascaded PLL's may not ALWAYS lock in all cases I believe.  Instead, use an external clock multi output driver ship and feed the PLL's from their appropriate input pins.

[Altera_Forum]

Thanks Guys, 

I thought so.  I got a 2.5 LVDS fan-out buffer on board I thought is useful to distribute to the top/bottom (Banks 4 and 7) to feed plls 5,6.   Looks like though, I have to AC couple and terminate’em externally for they are referenced to VCCINT ?    bst rgrds  Peter

[Altera_Forum]

Driving PLLs from a global clock network and cascading PLLs is basically supported by the Stratix II clock distribution scheme. So it's not generally necessary to supply external clocks to multiple inputs in parallel as required with Cyclone or Cyclone II. But it can achieve better jitter performance and lower delay skew. 

 The device handbook recommends to use different bandwidth settings with cascaded PLLs to avoid possible lock problems.