DSPBuilder signaltap tuning

[Altera_Forum]

Hi, 

I try to check correction of data from audio codec with signaltap on 2S60 DK. How can I decrease rate of data assigns to signaltap memory in dspbuilder model. I put signaltap block before and after rasampling block at simulink and after acquisition I receive same data. How can I do it in dspbuilder if at all? Thank you in advance. yan_w

[Altera_Forum]

You need to put in a Decimating Filter to Decimate the data to a lower sample rate: 

 IE if you codec is running at 192 Kbps, and you only need 48 Kbps, you can simply through 3 out of 4 samples away, but the 192 Kbps, may have some components that are above 24 KHz, so these would show up the output   A Decimating filter does 2 things, It basically is a low pass filter that kills anything that would violate the nyquest frequency of the new sample rate, an down samples the data to the new sampling rate.  Pete

[Altera_Forum]

Dear Anakha, 

First of all thank you help. I know in advance that the codec take out the data in 32KHz Fs that mean all samples in the middle are same ZOH (zero order hold). My question is how can I cause to signaltap node assigns data to memory more slowly than clock rate in dspbuilder model. Thanks yan_w

[Altera_Forum]

--- Quote Start ---   My question is how can I cause to signaltap node assigns data to memory more slowly than clock rate in dspbuilder model. Thanks yan_w  --- Quote End ---     Hi Yan: You can assign the any signal as a clock to Signal tape and all data is sampled on Signaltap's "CLK" so if you have a data enable that strobes the next stage, you can use this signal as the clock to signaltap, If you don't have one, you can create a simple clock divider and use that signal as well.    Pete

[Altera_Forum]

Hi Pete, Thank you very much again. It works properly.:) I made clock division by PLL and signaltap clock doesn't recognize PLL's clock. why? What the difference between clock divider and PLL principally?:confused:  Clock divider takes clock form CLOCK DRIVER chip? King regards, Yan 

[Altera_Forum]

Hi Yan: 

 During synthesis, sometimes if the clock is not driving other logic in you design, synthesis will remove and/or rename the signal, and then signaltap won't find it.  My guess is this is what's happening, When you build a simple clock divider outside of the PLL, it is made up a of register, that feeds back to itself, so it won't get optimized out. and since it's a register, it's easier to find.  Inherently there's nothing wrong with using a PLL generated divider.  Pete

[Altera_Forum]

Pete thank you very much ;)