non-application pin Model for Cyclone II

[Altera_Forum]

Is there something like a physical model, describing the behaviuor of such pins like Status, nConfig, MSEL and these ? 

 I am setting up a system to load and automatically reload FPGAs with new images from sources like e.g. flash. This whole process is a bit confusing, so I am using a simulation to check the timing. Bus behaviour is e.g. on topic: One ("big boss") FPGA loads data and moves it to the flash in chuncks and thus partly occupies the bus for short moments, another one uses flash data to configure FPGAs. All FPGAs use the same busses for data and addresses, so I am a bit concerned about the timeouts. For example, when do pins become active after configuration, and how quick do the switch intom tri state with a) nCE and nOE ?  I want to use such a model as a wrapper for my full design to have a complete toplevel simulation.  :o

[Altera_Forum]

Hello, 

 You can find information about Power UP, Reset, Configuration and initialization in a PDF named "configuring altera fpgas" .  About timing , you may look at device handbook (chapter "configuring ...."). Timing depends on device, options (fast programming, ...) and environment (power state, CRC checking...)  Other way, I am testing an home made "auto reconfiguration" in cyclone II by wiring a i/o pin to nconfig pin of the fpga itself trough a 1kohm resistor. Is there constraints with AS Programmation headers (pin 5) ? or other bad thing i have not seen ?   ++