ASI IP and Timing constraint.

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

ASI IP and Timing constraint.

983 Views

Maybe that's the right place:

The question is that the assignment to do on the PLL will be ignored by quartus II (v.8.0 sp1).

Please have a look on the other thread.

http://www.alteraforum.com/forum/showthread.php?t=3292

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.