Low Pass IIR filter using cyclone II FPGA

[Altera_Forum]

Hi everyone, 

I hava a task to implement low pass iir filter on cyclone II FPGA. The parameters of filter are the following: fp=5kHz; pass band frequency fs=8kHz; stop band frequency Fs=44kHz; sampling frequency amax=1db; maximal attenuation in a pass band anim=50db; minimal attenuation in a stop band as a refferent filter I use Chebyshev filter.  After a few calculation I got N=7 for a order of my filter. After that, I got the transffer function H(z) = 8*10^(-6)*(1+z)^7/(z^7-5.515z^6+13.761z^5-20.023z^4+18.29*z^3....  As you see I have to implement multiplication of usigned numbers.  I need advice: which is the best way to implement this recursive formula? I also need to know how many bits-wide operands must be and how to implement multiplication.  Thank you very much for your efforts to help me ! Bojan

[Altera_Forum]

Than you for advice Micheel but I must to use Cyclone II FPGA this time and VHDL programming language. So... if you have ideas please share with me. 

Thank you very much, Bojan

[Altera_Forum]

U.Meyer-Baeses digital signal processing with fpga is a profound DSP textbook with a detailed IIR filter chapter. It also has VHDL examples. 

 I can't see, that the filter is defined recursively in your example (and it probably shouldn't be). But it's strongly recommended to scale the coefficients to a fixed point representation to allow a FPGA suited filter implementation with signed signals. Some filter tools, e. g. Nuhertz Filter Solutions, perform this operation in filter design automaticly. Also MatLab/Octave can do, of course.

[Altera_Forum]

Yes, filter is recursive and the 7th order. 

b0y(n)=a0x(n)+a1x(n-1)+...+a7x(n-7)+b1y(n-1)+b2y(n-2)+...+b7y(n-7)  I want to know which is the best way to represent coefficients ai, bi, i=0...7? Maybe like a signed number with a fixed point? And with how many bits? Is it 16bits enough? Thank you for you effort, Bojan

[Altera_Forum]

The resoution of the coefficients (16 bits or less or more) depends on the wanted accuracy of the filter output, e.g. if you have a mask which the filter must fit. So I suggest you to use Matlab/Octave or any other math tool to perform a fixed-point finite-resolution simulation. You will be able to insert your coefficients with 16bits (or different) and see the result on the output. The minimum needed resolution will be the one which fits your output mask. After that you can go to the the FPGA resolution.

[Altera_Forum]

--- Quote Start ---  Yes, filter is recursive and the 7th order. b0y(n)=a0x(n)+a1x(n-1)+...+a7x(n-7)+b1y(n-1)+b2y(n-2)+...+b7y(n-7)  --- Quote End ---   The filter is recursive has any IIR filter, but the formula is a standard form of z transfer function, I wouldn't regard it as recursive.  Coefficient resolution utilisation is ineffective in the standard form, cause a large range has to be covered. I found 18 bit resolution (13.5) is required for an acceptable frequency response in the present case, 16 Bit has an considerable magnitude error. In contrast, a cascaded form using first and second order building blocks achieves similar results with only 10 Bit (9.1) coefficient resolution.

[Altera_Forum]

Use the direct ii-transpose structure. Not the direct form. 

 It's ideal on fixed-point IIR filtering, it minimizes quantization errors better than others.  In order to improve the performance use a rounding escheme.  Download the Mentor Graphics C header files ac_datatypes to test the arithmetic.

[Altera_Forum]

Ok guys, 

I did just like you told me: maximum of my ai, bi, i=1,...,7 coeff is -20.023... I did the simulations and 18 [6.12] coefficients bit resolution fits my output mask. So I overcome the problem with coeff representation and I represent the coeff in a two's complement representation with 18bits (6.12).  I'm trying to understand how to perform multiplication of sampled digitalized signal x(n-i) and coefficient ai, bi. How to perform the multiplication when I have coefficient ai, bi in a two's complement representation with a fixed point and digitalized semple (output of A/D converter) x(n-i) which is not in a two's complement and don't have fractional part. If you understand my problem and have any idea please advice me. Thank you very very much! Bojan

[Altera_Forum]

The transition from 2s complement to unsigned is performed by inverting the MSB (this is the same as adding half dinamic range), and everything works if the original 2s complement signal is not overflowing or underflowing. 

So before your multiplication you have to perform the conversion and your multiplication will work in unsigned mode.

[Altera_Forum]

OK, you gave me idea. I'will perform multiplication with all positive coefficients, and after multiplication I'will perform substraction instead of addition. 

a1*x(n-1)-b1*y(n-1) =(a1*x(n-1)) - (b1y(n-1)) ! So my coeff will be +20.023... And now... how to perform multiplication of 18bit sampled digitalized value of input signal x and coefficient which have 18bits (6bits for number and 12bits for fractional part - 6.12)? Sorry if I ask too much and if I ask nonsenses ! Bojan

[Altera_Forum]

It is a classical problem of fixed point mathematics. The ideal Altera tool for your job is the altmult_accum megafunction which multiplies and accumulates in a single module. 

The fractional number should be transformed to integer numbers (you may use Matlab/Octave for a simulation before) and the result should be scaled back considering the multiplication factor that you have applied to one of the operands before the multiplication. If you need help about the Altera megafunction you can have a look at:  http://www.altera.com/literature/ug/ug_altmult_accum.pdf

[Altera_Forum]

altmult_accum megafunction is mapped to Cyclone II hardware multiplier blocks plus regular logic for accumulator, it doesn't result in a different DSP implementation than generic HDL code. But you may find it helpful to structurize your code.

[Altera_Forum]

Hello people, 

I saw mult_accum.pdf file you suggested me. Ok, there is some Wizard which guide me through the process of creating multiplier. Is there any chance to see the VHDL code of that multiplier created by the wizard? I didn't see that multiplier can perform multiplication with fixed point unsigned numbers. Please advice, Regards, Bojan

[Altera_Forum]

altmult_accum is generating AHDL (*.tdf) rather than VHDL code. It has some useful features as saturation logic but no particular support for fixed point (fractional) numbers. In multiplication, fiexed point means nothing but apllying a shift factor to the result, so no particular support is needed, I think.

[Altera_Forum]

1 . If your N bits ADC is not two's complement: 

  add to the conversion result 2^(N-1) in order to convert to signed.   2. multiply de x(n-i) sample with filter coefficient, result will be : N + N_coeff   the simplest way to round is with an N_frac bits rigth arithmetic shifting. N_frac es the fractional part length.

[Altera_Forum]

Hello people... 

In attachment I gave you block diagram of my filter design. And I want to ask you something... I will multiply my 18bits sampled input signal with 18bits fixed point coefficient (6.12). [x(n)*a]. Result will be 36bits wide, and 12 LSBs of the result are fractional part, right. Can I exclude these 12 fractional bits from further calculation? If my output from FPGA must be 18bits wide how to threat 24 bits of multiplication result? I pick up just 18 LSBs? If I get at least one 1s on 6 MSB positions of 24 bit multiplication result I should pick up 111111111111111111 for the result, right? Please advise me If my way of thinking is all right? Thank you in advance! Bojan

[Altera_Forum]

Hi Bojan. 

First of all let's suppose that your multiplier has an unsigned result. Everything that you want to implement into your FPGA can be simulated in Matlab before. The final goal is to exploit the full 18bits dynamic range of your final DAC. So you have to analyze the output of your multiplier and see what dynamic range has its output (this will depend on the filter input and on the coefficients). The 18 bits that you have to send to your DAC (supposing that the DAC accepts unsigned inputs) are the first MSBs starting from the highest bit that shows a variation at the multiplier output. In this way your DAC output will be maximized. Once you have simulated everything in Matlab you can design your truncation block at the multiplier output.

[Altera_Forum]

Hi, 

Is it better for me to choose AD converter which gives a signed 2's complement result of coversion? Bojan

[Altera_Forum]

There is no problem with the format, you can always perform a format conversion at every point where it is needed. Just choose the ADC and the DAC taking care about their resolution, linearity and S/N ratio. The rest is simple logic.

[Altera_Forum]

--- Quote Start ---  So you have to analyze the output of your multiplier and see what dynamic range has its output (this will depend on the filter input and on the coefficients).  --- Quote End ---   I expect, that the filter should have a defined nominal gain rather than determining the gain empirically. That's also the concept behind using fractional number formats to my opinion: Having a defined filter function and choosing a signal and coefficient scaling  from known signal characteristics. If filter blocks with a gain different from unity are cascaded, there is a danger of over- or underflow. It should be checked either with typical signals in a hand calculations or at best in a fixed point simulation.    --- Quote Start ---  If my output from FPGA must be 18bits wide how to threat 24 bits of multiplication result? I pick up just 18 LSBs?  --- Quote End ---   Using a fixed 6.12 scaling through the signal chain means discarding 6 high and 12 low bits after each multiplier. For the discarded high bits, a saturation logic should be used, including correct sign handling of course.  Two additional points: A resolution of 12 fractional bits may be too low for the low frequency end of filter characteristics. It may also result in inacceptable high quantization noise at low input levels.

[Altera_Forum]

Folks, 

One question is bothering me this time...:confused: concerning LowPass filtet of course. I have input signal range within, let's say, x(t)[-5,5V], and I've designed filter transfer function with some coefficients. I sample x(t) in a specified moment of time and I perform filter calculations using that sample and a some previous samples. Does it means that each calculated output y(t) must be within a range of my input signal x(t) or not?