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Hello All,
I am using Altera Max700AE CPLD device for my design. In my design I have two clocks one with 45 Mhz and another with 4 Mhz. 1) I can not able to set setup and clock to out settings fro each clock 2) I want to exclude one path which I know it will not meet the timing as the synchronized outputs are used as input to some on nand gates and multiplexers to generate final output, I can not able to do exclusion of path (false paths) I am using clasic timing analyser. Timequest anylser is not supported for this device. And all my constraints are presented in .qsf file. I have tried wih the command set_false_path. I have tried set_timing_cut_assignment. Can any body help me out in resolving this issue. best regards, Pavan MLink Copied
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