Quartus II 7.2 & Declaring bus range problem

[Altera_Forum]

I've design my project with some .vhd and .bdf files without any error or warnings but in "synthesis and elaborate" I face to this problem frequently: 

 Warning: Undeclared parameter MTU  Error: Bus range for signal "port "label_out[MTU-1..MTU-32]" (ID FWD_Input_BDF:inst1)" must be a number    but I've specified that in the .vhd file in generic clause for example like this: generic (MTU :integer:=8192); and I've updated my designs and block/symbols frequent times but nothing has changed I couldn't find somewhere else for declaring the value

[Altera_Forum]

by right-clicking on the error and help> it says: 

"specified in your .bdf or .qdf but not declared"  how can i declare these parameters I've specified them in my vhdl file as I said before (generic clause)

[Altera_Forum]

I don't see a problem. When you create a symbol file for your VHDL component, the generics are automaticly used as block parameters, you can show them in the schematic. You can change the parameter value in the schematic according to your needs, either use a fixed value or a global parameter as in my below example that simply instantiates the gray_counter from Quartus VHDL templates.

[Altera_Forum]

Yes all thing seems to be correct.... in vhdl file and block/schematic 

 I've design some vhdl files and some .bdf file from them but with top-level design but without design hierarchy but I think that I need to compile the project to be able to assign hierarchy to files automatically or manually I don't know.... but here is the complete report: ========================= Date: September 20, 2008 Project: FWD_Comp Info: ******************************************************************* Info: Running Quartus II Analysis & Elaboration  Info: Version 7.2 Build 151 09/26/2007 SJ Full Version  Info: Processing started: Sat Sep 20 19:20:50 2008 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FWD_Comp -c Rev3  --analysis_and_elaboration Info: Found 2 design units, including 1 entities, in source file Ser.vhd  Info: Found design unit 1: Ser-Ser_arch  Info: Found entity 1: Ser Info: Found 1 design units, including 1 entities, in source file FWD_Comp.bdf  Info: Found entity 1: FWD_Comp Info: Found 2 design units, including 1 entities, in source file Pkt_Mgr_Shift_Reg.vhd  Info: Found design unit 1: Pkt_Mgr_Shift_Reg-Pkt_Mgr_SR_Arch  Info: Found entity 1: Pkt_Mgr_Shift_Reg Info: Found 2 design units, including 1 entities, in source file Pkt_Mgr_Detector.vhd  Info: Found design unit 1: Pkt_Mgr_Detector-Pkt_Mgr_Detector_Arch  Info: Found entity 1: Pkt_Mgr_Detector Info: Found 2 design units, including 1 entities, in source file Deserializer_Sync_Shift_Reg.vhd  Info: Found design unit 1: basic_shift_register-rtl  Info: Found entity 1: basic_shift_register Info: Found 1 design units, including 1 entities, in source file Pkt_Mgr.bdf  Info: Found entity 1: Pkt_Mgr Info: Found 1 design units, including 1 entities, in source file FWD_Input_BDF.bdf  Info: Found entity 1: FWD_Input_BDF Info: Found 2 design units, including 1 entities, in source file binary_counter.vhd  Info: Found design unit 1: binary_counter-rtl  Info: Found entity 1: binary_counter Info: Found 2 design units, including 1 entities, in source file Des.vhd  Info: Found design unit 1: Des-Des_Arch  Info: Found entity 1: Des Info: Found 2 design units, including 1 entities, in source file BQ_data.vhd  Info: Found design unit 1: BQ_data-arch_bq_data  Info: Found entity 1: BQ_data Info: Found 2 design units, including 1 entities, in source file BQ_counter.vhd  Info: Found design unit 1: BQ_counter-arch_bq_counter  Info: Found entity 1: BQ_counter Info: Found 1 design units, including 1 entities, in source file CAM_RAM_BDF.bdf  Info: Found entity 1: CAM_RAM_BDF Info: Elaborating entity "FWD_Comp" for the top level hierarchy Warning: Undeclared parameter MTU Error: Bus range for signal "port "label_out[MTU-1..MTU-32]" (ID FWD_Input_BDF:inst1)" must be a  number Warning: Undeclared parameter MTU Error: Bus range for signal "port "label_out[MTU-1..MTU-32]" (ID FWD_Input_BDF:inst1)" must be a  number Warning: Undeclared parameter MTU Error: Bus range for signal "port "data_out1[MTU-33..0]" (ID FWD_Input_BDF:inst1)" must be a number Warning: Undeclared parameter pkt_len_counter Error: Bus range for signal "port "counter_out6[pkt_len_counter-1..0]" (ID FWD_Input_BDF:inst1)" must  be a number Error: Can't elaborate top-level user hierarchy Error: Quartus II Analysis & Elaboration was unsuccessful. 5 errors, 4 warnings  Info: Allocated 154 megabytes of memory during processing Error: Processing ended: Sat Sep 20 19:20:59 2008 Error: Elapsed time: 00:00:09  ==========================================

[Altera_Forum]

I've fixed the problem by this:  

Setting>Default Parameters>  and then redefine MTU and pkt_len_counter  I don't know why but it is working.  after this I encounter another strange problem:  Error (10531): VHDL Variable Declaration error at Ser.vhd(56): variable declared outside subprogram or process must be a shared variable  why? I've fix this problem by using shared varibale:   architecture Ser_arch of Ser is signal label_mem : std_logic_vector((Label_Width-1) downto 0); signal data_mem : std_logic_vector((MTU-1-32) downto 0); signal counter_mem : std_logic_vector((Counter_Width-1) downto 0); signal prtc_flag : std_logic; -- Packet ready to Combine -- prtc_flag uses as signal and it's just the AND of 4 ports. variable sr : unsigned((SOF_len+Label_Width+MTU+SOF_len-1) downto 0); variable cnt : integer; variable tmp : std_logic_vector((SOF_len+Label_Width+MTU+SOF_len-1) downto 0); -- =====================function decleration======================= -- crating function to convert the std_logic_vcetor to integer: function TO_INTEGER_stdvect (ARG: std_logic_vector) return NATURAL is constant ARG_LEFT: INTEGER := ARG'LENGTH-1; alias XXARG: std_logic_vector(ARG_LEFT ...... ......    Why this is necessary to define the shared values I just use this variable in current architecture...  sth strange...

[Altera_Forum]

--- Quote Start ---  Why this is necessary to define the shared values I just use this variable in current architecture...  sth strange...  --- Quote End ---    I wonder what you are trying to achieve with variables? I guess, most VHDL programmers don't even know, that shared variables exist. They follow the simple rule, that variables can be used in processes and subprograms, as written in most VHDL textbooks. You have to read the full IEEE VHDL specification to learn about shared variables. Apparently, no one misses them, normally.

[Altera_Forum]

yes I'm not a professional HDL Coder 

this is my first relevant project to HDL designing and I'm also hasn't read any book yet about VHDL....just some brief article and a VHDL Quick Reference.... I like to learn a new language with jumping in middle of it... I would be appreciated if you tell me why... after all I'll search about the difference between shared or not shared variable...but from a C perspective I like local variables more... Thank   ------------------------------------------ shared variables hasn't considered enough in text books also, I had one ref book from MIT but it hasn't covered this concept yesterday I search through its Index but couldn't find sth valuable about this.

[Altera_Forum]

I have to agree with FvM here. 

 I have never used (or even seen!) a shared variable in VHDL. They sound dangerous!

[Altera_Forum]

--- Quote Start ---  [LIST] VHDL87 limited the scope of the variable to the process in which it was declared. Signals were the only means of communication between processes, but signal assignments require an advance in either delta time or simulation time. [/LIST][LIST]VHDL '93 introduced shared variables which are available to more than one process. Like ordinary VHDL variables, their assignments take effect immediately. However, caution must be exercised when using shared variables because multiple processes making assignments to the same shared variable can lead to unpredictable behavior if the assignments are made concurrently. The VHDL �93 standard does not define the value of a shared variable it two or more processes make assignments in the same simulation cycle. [/LIST]  --- Quote End ---    from here: http://www.people.vcu.edu/~rhklenke/tutorials/vhdl/modules/m13_23/sld029.htm [LIST] [/LIST]

[Altera_Forum]

If you are talking of VHDL code for simulation, the behaviour it's very similar to C-programming. The code is interpreted sequentially and you can assign a value to a variable here and there, as long it is anywhere in the namespace.  

 In synthesizable VHDL, a variable can mean different things. It can be a physical signal, particularly the state of a register. If you define a counter based on a variable, it's just this. Or a variable can be a kind of virtual signal, e. g. a loop variable in an iteration or an intermediate result. It has no physical reality as such and is transformed to something different by the compiler.  As a simple fact, a register can be assigned only one value at a time, also it can have only one valid clock. For this reason, a physical signal can be assigned only in one process or only once in sequential code. Shared variables can't change this facts basically.

[Altera_Forum]

The guys are pretty spot on here. I find variables can be useful in processes to help sort out intermediate calculations - be damn careful with them as they could synthesise into a register r a wire depending on the order of your code. 

 As for shared variables:   --- Quote Start ---  ...but from a C perspective I like local variables more...  --- Quote End ---   Personally I find it really unhelpful to compare a hardware description language with a software language because they are fundamentally describing different things and are therefore so very different in their nature. Please don't think that this is patronising but remember that you are not writing C; you are describing hardware: gates, registers, counters, adders, multiplexers etc. What lump of logic are you trying to describe with a shared variable? What are you expecting this to synthesise into?  If you are starting out with VHDL then, I would say, use signals. You can progress quite happily without using variables at all. Use variables when you understand what they will synthesise into and how the order of your code will affect this. I think it's probably fair to say that for synthesisable code you probably will never have to use variables though.  I have only ever used shared variables once - in a high level behavioural bus model to communicate between different procedures in a package. Personally if you are starting out with VHDL I would forget about shared variables - you'll get a very very long way before you need them and when you do, it will be obvious why. I wouldn't be surprised if most VHDL / FPGA designers never feel the need to use shared variables.

[Altera_Forum]

Thank guys 

till now I've used variables when they have not any physical meaning and as a synthesizer guide...when using signals are not required or have some problem with types and different operators.