Quartus 7.2 lost signal in correct assignment

Altera_Forum · ‎09-22-2008

here is my code in brief:

I've problem with the red line.

==============================================

 
-- Serializer 
-- sadid sahami 
 
library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
use ieee.numeric_std.all; 
library altera; 
use altera.altera_internal_syn.all; 
 
 
entity Ser is 
    generic( 
        MTU : integer:=8192; 
        Counter_Width : integer:=14; 
        Label_Width : integer:=32; 
        SOF_len        : integer:=8; 
        SOF    :std_logic_vector(7 downto 0):=B"00001111" 
    );  
    port( 
        input_label : in std_logic_vector((Label_Width-1) downto 0); 
        Data_in        : in std_logic_vector((MTU-1-32) downto 0); --serializer 
        Counter_in    : in std_logic_vector((Counter_Width-1) downto 0); 
        clk         : in std_logic; 
        ser_out        : out std_logic; 
        dhs_flag    : buffer std_logic;     
        d_flag        : in std_logic;  
        c_flag        : in std_logic;  
        l_flag        : in std_logic   
        ); 
end entity Ser; 
     
architecture Ser_arch of Ser is 
    signal label_mem    : std_logic_vector((Label_Width-1) downto 0); 
    signal data_mem        : std_logic_vector((MTU-1-32) downto 0); 
    signal counter_mem    : std_logic_vector((Counter_Width-1) downto 0); 
    signal prtc_flag    : std_logic;    -- Packet ready to Combine 
    shared variable sr            : unsigned((SOF_len+Label_Width+MTU+SOF_len-1) downto 0); 
    shared variable cnt        : integer; 
    shared variable tmp        : std_logic_vector((SOF_len+Label_Width+MTU+SOF_len-1) downto 0); 
     
     
    -- =====================function decleration======================= 
    -- crating function to convert the std_logic_vcetor to integer: 
    -- .. 
    --    =================================================================== 
     
     
    -- ===============function decleration============================== 
    -- a function to change unsigned value to std_Logic_vector 
    -- .. 
    --    =================================================================== 
         
    -- ================function decleration============================== 
    -- a function to change std_logic_vector to unsigned 
    -- .. 
    --    =================================================================== 
     
 
    begin 
        process(clk) 
            begin 
            prtc_flag<=dhs_flag and d_flag and c_flag and l_flag; 
            if (rising_edge(clk) and prtc_flag='1') then 
                -- load data for serializing: 
                label_mem <= input_label; 
                counter_mem <= Counter_in; 
                data_mem <= Data_in; 
                dhs_flag<='0'; 
            end if; 
            cnt:=to_integer_stdvect(counter_mem+1); 
            tmp := SOF & label_mem & data_mem  & SOF;  
            if(cnt/=0) then 
                ser_out <= tmp(0); 
                sr := to_unsigned_stdv(tmp);  
                sr := sr srl 1; 
                tmp := to_stdlogicvector_un(sr); 
                cnt := cnt-1; 
            end if; 
            if(cnt = 0) then 
                dhs_flag<='1'; 
            end if;                 
        end process; 
 
end architecture Ser_arch;

Error (10344): VHDL expression error at Ser.vhd(141): expression has 8208 elements, but must have 8240 elements

this is means that the label_mem dosn't apply to temp whay? I double check the code why?

I've also use tmp as signal but nothing change or check the .qbf file for Ser's inst2's input : incoming_label has 32 bit length.

by this code modification:

tmp1 := SOF & Label_mem;

tmp2 := data_mem & SOF;

tmp := tmp1 & tmp2;

this error appears:

Error (10344): VHDL expression error at Ser.vhd(144): expression has 8168 elements, but must have 8200 elements

this means 2 label and one SOF has been lost (32+32+8

I've also try direct numerical declaration but nothing change....

what about using concatenation....8240 vs 8202...

Altera_Forum · ‎09-22-2008

You have declared a signal as follows

signal data_mem : std_logic_vector((MTU-1-32) downto 0);

I think the MTU-1-32 might be causing your length difference.

Shouldn't

shared variable tmp : std_logic_vector((SOF_len+Label_Width+MTU+SOF_len-1) downto 0);

be declared as

shared variable tmp : std_logic_vector((SOF_len+Label_Width+(mtu-32)+SOF_len-1) downto 0);

Rgds

Altera_Forum · ‎09-22-2008

I'll test it. Now I can't test it.

thank