Newbie: Declaration in AHDL

[Altera_Forum]

Hello, 

how does the declaration of an OUTPUT work in AHDL? Do I have to declare it again in the VARIABLE-Section? I wrote four examples, can you tell me which one is right and which is wrong?  Thank you, Philipp   SUBDESIGN Test1 ( S : OUTPUT; Takt : INPUT; )  VARIABLE S : DFF;  BEGIN S.clk = Takt; S = ....; END -----------------  SUBDESIGN Test2 ( S : OUTPUT; )  VARIABLE S : NODE;  BEGIN S = ....; END ----------------------    SUBDESIGN Test3 ( S : OUTPUT; )  VARIABLE   BEGIN S = ....; END -------------------------     SUBDESIGN Test4 ( S : OUTPUT; Takt : INPUT; )  VARIABLE T : NODE; S : DFF;  BEGIN S.clk = Takt; T = ....; S = T; END

[Altera_Forum]

It depends what you need, but if I can give you a suggestion stop using AHDL that is a proprietary altera language and move to VHDL or Verilog. 

That's most true if you have to start learning it.  To answer: Test 1: your output is registered so it's an output of a flip flop. Test 2: your output is pure combinatorial it's a point of a net Test 3: I don't remember if it compiles but in that case it depend from the assignment. Test 4: you take the point T of a netlist as the input of a flip flop whose output is your S.

[Altera_Forum]

Thanks, I have to use AHDL in the company I work in.

[Altera_Forum]

Assuming "..." is replaced by a valid expression, they all look right, and should all compile, except that Test3 has an empty variable section. Just remove the VARIABLE keyword and it should be ok. 

 Test1 and Test4 are equivalent, as are Test2 and Test3.  So, in answer to your question, no, you do not need to re-declare outputs in the variable section. However, if you want the output to be registered, you do need to declare the output register as you have done in Test1.