Cyclone II : Configuration through Embedded JTAG

[Altera_Forum]

Dear All,  

 i am new to the FPGA world.  I am using FPGA for signal processing. i have the *.rbf file.  i want to load this file into FPGA SRAM.this the following step i m performing:   1. i am loading the *.rbf file (un compresed version) into flash memory.  2. reading one bye and wrting it to FPGA through JTAG interface between microcontroller and FPGA. microcontroller is genrating clock. 3. i have implemented JTAG state machine on microcontroller.   my configuration is as follows: MSEL1 =GND MSEL0 = HIGH CONF_DONE = HIGH (VDD 3.3 Volt)   I am able to read ID code after giving instruction ID_CODE as 0x20B30DD. I also get the configuration sucessful indiction (as given in JRunner software) After Reset i am giving config instruction, then switching to user mode.  But LED connected to FPGA is not working at all. BUT i am able to read DEVICE_ID again.   I am not able to figure out what is going wrong.    ..  I want to know is there any thing that i should take care for *.rbf file.   need help.   Thanks.   Regards, vidya

[Altera_Forum]

Are you using a custom board or an Altera evaluation board?

[Altera_Forum]

no it is a custom board not altera board.  

harware component is fine because when in AS mode (MSEL1=MSEL0=GND) all the LED works fine.

[Altera_Forum]

I can't determine from the information you gave, if you are processing the *.rbf file correctly and using the right JTAG commands. Do you follow any Altera documented method? Most embedded systems I know, that are configuring the FPGA from a microcontroller or logic device are using PS or PP.

[Altera_Forum]

I am using JRunner source code as refrence. 

   my goal: I want to configure FPGA with JTAG interface.  I have downloaded complete uncompressed RBF in external FLASH interfaced with microcontroller. I am reading one byte from Flash and sending that byte on FPGA_TDI pin with LSB first.   problem: 1. How one should gerate clock? i am genrating it when i am riting byte to FPGA_TDI , toggling Microcontroller TCK pin Low to high transition.   writeport_data(unsigned char data) { if (data) write 1 to FPGA_TDI pin else write 0 //genrate Riging Edge clock TCK_Pin = Low delay(20); TCK_Pin = High delay(20); }   2. I am not able to figure out what is problem with my code. 3. Is there ant method for reading *.rbf file. any CRC check is there, if it is there how to verify it in code.  4. How to verify the all the bits are written properly?   present status of my code: I am able run JTAG state machine correctly.   when ever i am sending the JTAG instruction on FPGA_TDI pin with rising clock edge, i am getting 10 bit sequence of "1010101010"(0x155) on FPGA_TDO pin. As mentioned in the Altera document(Cyclone II device Handbook volume-1 page no - 14-17).   when i send Read DEvice ID it gives the correct data on FPGA_TDO pin as mentioned earlier.   when i am sending the Programm Instruction it doesn't work.  how i m doing it is mention below in steps: 1.Got to RESET/RUN_IDLE state 2. Go to SHIFT_IR state 3. Send 10 bit Instruction Byte (0x002) 4. Go to SHIFT_DR state  5. send complete *.rbf file date with LSB bit first 6. sned 299 additional clock cycle (as mention in the Altera HAndbook page no-13-56 2nd paragraph) to initialize Cyclone II device. 7. then exit SHIFT_RD state.   after this switch to user mode by sending JTAG instruction 0x003.   when i read and write any register in FPGA it some time return 0x06, or 0xFF. and LED is not working at all.   but when it is programmed through JTAG ByteBlaster it works fine.   system pin configuration details: my system has one AT91R40008 microcontroller and one Cyclone II FPGA((EP2C20F256). Four I/O pin of micro is connected to the JTAG port of FPGA. nCONFIG pin is pulled up with 10K ohm registor. CONFG_DONE pin is pulled up with 1K ohm registor. I am keeping MSEL status as given in Altera Document. MSEL1= to GND MSEL0 to Vcc.

[Altera_Forum]

is there any documented method from Altera for configuring FPGA with JTAG instruction. 

 which says the write frollowing instruction , following out put will come.  method for verifying proper configurtaion done or not.

[Altera_Forum]

The Configuration Handbook doesn't show, how JTAG configuration is carried out, it's assuming a JAM configuration file rather than rbf and using the embedded JAM player software. I'm not aware of the wire protocol with JTAG configuration, but I think it's different from just streaming out a rbf file. (A rbf file, by the way, has a header, that would be skipped when using it e. g. for PS configuration). 

 The embedded JAM player sources and related information can be found at Altera website. As far as I remember, there are a text based, JAM and a binary JBC format. Both are containing sequences of JTAG instruction together with the data, which makes them very unhandy compared to simple binary configuration bitstreams, they are mainly used in multiple vendor production enviroments. A native embedded JTAG programmer, directly processing bitstreams, most likely isn't provided by Altera.

[Altera_Forum]

It looks quite correct what you are doing. Some comments concerning your questions: 

1. How one should gerate clock? You do it nearly perfect. Apply data, wait, apply rising clock edge, wait, apply falling clock edge. 3. Is there ant method for reading *.rbf file. any CRC check is there, if it is there how to verify it in code.  No, rbf is really raw. If you change 1 single bit you cannot figure that out but the FPGA will refuse to being configured 4. How to verify the all the bits are written properly? No way.  It seems that you have donwloaded the jrunner source code and ported that to the embedded controller. I think there are some comments in that source code telling that for particular devices some bits at the very beginning must be disregarded. Maybe you should read the original source code in detail.

[Altera_Forum]

In JTAG,  

 what ever is transmitted on FPGA_TDI port , same data is can be collected on FPGA_TDO port in the next clock cycle.   Is it correct in case of transmitting the binary data from RBF file?   when I read data from FPGA_TD0 pin i get the byte but it is shifted one bit. some time it is 2 bit shifted.    i am incrementing counter if i get any mismatch and there is lots of byte that doesn't match with TDI port data. can you suggest possible reason for that?   Is there any Limit for toggling I/O pin? what is the Max/Min clock frequency for FPGA configuration with JTAG interface?

[Altera_Forum]

Vidya, 

 I don't know what is supposed to be sent out at TDO during device configuration. But if the data coming out at TDO is the same as this one sent to TDI but after ONE OR TWO clock cycles than this looks somewhat weird. I like to recommend that you write a small test program to test the reliability of the JTAG communication between uC and FPGA. Use the bypass instruction to select the bypass register in the FPGA as the TDO source. So TDO should drive the data sent into TDI with one clock delay. Send several million random bits and use you alredy implemented error counter to see if the communication is stable. Concerning your questions: I cannot imagine that you can reach the limts with a micro controller executing some firmware. No way. You will hurt setup/hold requirements if you change TDI/TMS with the same instruction that causes the rising clock edge. But, according to you description, this is not the case.

[Altera_Forum]

I have to correct my statement regarding JTAG configuration streams. I was thinking of the JAM player method used for PLD prgramming, however JTAG FPGA configuration is actually sendng a cotinuous binary configuration stream (LSB first), as documented in the Jrunner source code. But a 44 byte header has to be stripped before, as said. 

 The TDO signal during configuaration isn't specified and not checked normally, I think. Cause the TDO stream is send to the configuaration controller rather than a scan chain, I would expect that's it's delayed in PROGRAM state by one clock as in BYPASS. Watching a variable delay may actually indicate incorrect JTAG timing.  The complete JTAG timing specification for Cyclone II is given in the device manual. With cyclone II,up to 25 MHz JTAG clock is possible.