Clocked video output

[Altera_Forum]

Hello 

 I'm trying to use the Clocked Video Output IP with the SOPC builder I need to output a NTSC (4:3 525 lines) video with separate sync signals. To create the separate sync signals the wizard needs the following parameters: Field 1 Horizontal sync (pixels) Horizontal front porch (pixels) Horizontal back porch (pixels) Vertical sync (lines) Vertical front porch (lines) Vertical back porch (lines)  Field 0 F rising edge line F falling edge line Vertical blanking rising edge line Vertical sync (lines) Vertical front porch Vertical back porch  I've tried different combinations (which I thought were OK) but couldn't get the video correctly sync'd. Anyone knows the correct values?  Thank you Thiago

[Altera_Forum]

There is a spreadsheet available to calculate these values from VESA: 

 www.vesa.org/public/cvt/cvtd6r1.xls  See if it helps you.  Jake

[Altera_Forum]

Have you tried to read: 

 http://www.altera.com/literature/ug/ug_vip.pdf  It seems that there are suggestions for these parameters there.

[Altera_Forum]

Thank you Jake and OrchestraDirector 

 I did try the configuration suggested in the CVTd6r1.xls but it still wouldn't work At the ug_vip.pdf I didn't find any suggestions, could you point me the exact location OrchestraDirector?  Anyone used this Clocked_Video_Output with separate sync signals? Did it work? What configuration did you use?  Thank you  Thiago

[Altera_Forum]

I thought that the suggestions at page A-13 and A-14 could be useful for your purpose.

[Altera_Forum]

Oh, these are only the default values and unfortunately the separate sync values are zero in this mode 

 Thank you!  Thiago

[Altera_Forum]

--- Quote Start ---  Hello  I'm trying to use the Clocked Video Output IP with the SOPC builder I need to output a NTSC (4:3 525 lines) video with separate sync signals. To create the separate sync signals the wizard needs the following parameters: Field 1 Horizontal sync (pixels) Horizontal front porch (pixels) Horizontal back porch (pixels) Vertical sync (lines) Vertical front porch (lines) Vertical back porch (lines)  Field 0 F rising edge line F falling edge line Vertical blanking rising edge line Vertical sync (lines) Vertical front porch Vertical back porch  I've tried different combinations (which I thought were OK) but couldn't get the video correctly sync'd. Anyone knows the correct values?  Thank you Thiago  --- Quote End ---    Hi Thiago,  what output format are driving with the CVO? DVI, VGA?  Could you post the settings you are using or a screenshot of the settings you are using?  Also what are you driving the CVO with? It needs to be fed with interlaced video for NTSC output to work. It can't create interlaced video from a progressive input.  Regards, Gareth.

[Altera_Forum]

Hello Gareth! 

 I'm using the Test Pattern Generator (from Altera) to feed the clocked video output. I configured it to generate a 720x486 pixels interlaced colorbar (F0 synchronized). The colorspace is YCbCr with 10 bits per color space using 4:2:2 sampling. The clocked video output is configured like this: Image Width: 720 pixels Image Height: 486 lines Bits per pixel per color plane: 10 Number of color planes: 2 Color plane transmission format: parallel Interlaced video checked Pixel fifo size: 720 pixels Sync signals: on separate wires  The synchronization signals settings are what I need to know  Using embedded sync signals the video was output perfectly, but I really need the external sync signals to drive other components  Thiago

[Altera_Forum]

Hi Thiago, 

   --- Quote Start ---   The synchronization signals settings are what I need to know  Using embedded sync signals the video was output perfectly, but I really need the external sync signals to drive other components  Thiago  --- Quote End ---    One issue you may have run into is that the NTSC format is actually has 487 lines (f0 - 244, f1 - 243). To get the same frame as the embedded syncs mode (minus the bt656 embedding) put the values in with no fp or bp:  active width = 720 active height = 487 horizontal sync = 138 horizontal fp = 0 horizontal bp = 0 vertical sync = 19 vertical fp = 0 vertical bp = 0 f0 vertical sync = 19 f0 vertical fp = 0 f0 vertical bp = 0 f rising edge line = 266 f falling edge line = 4 vertical blanking rising edge line = 264  There's a bug in the GUI where the 'active picture line' gets greyed out in seperate sync mode. Make sure it is set to 20 (switch the embedded sync mode to make it editable).  This mode won't output bt656, if you need that you'll have to embed the syncs yourself. Do you require an embedded sync mode where you can see the sync signals v,h,f?  The test pattern generator doesn't support odd numbers of lines in interlaced format though so you won't be able to get it to output 487 lines.  Regards, Gareth.

[Altera_Forum]

Wow, thank you so much Gareth! 

Worked perfectly!  Where did you get these values from? I'll need to output HD (1080i) later so it would be useful for me to know how to get (or calculate) them  Thanks again!  Regards Thiago

[Altera_Forum]

Hello everyone, 

 I desperately need help with getting my embedded sync bt656 clocked out IP to work.  I have connected the test generator module found in the VP 8.0 reference example, and connected it to the Clocked Out video ip.  Then connected the Video output 8 bit bus to my ADV7171 video IC.( which has been tested with its internal color bar.)  The test generator is set to send := 422 ycrcb 720 by 486  The Video Clocked out IP is set to Embedded sync mode, 720 by 486 active picture and 8 bit , 2 symbols per beat and interlaced.  synce field one is Active Picture line=20 Horizontal Blanking =138 Vertical Blanking = 20  Field zero F rising=266 F falling =4 vertical blanking rising edge line =264 vertical blanking =19  All I end up getting is a black screen, and when brightness is turned up it is light green vertical lines. Please can some one help me with this problem , it will be greatly appreciated.  regards, Nadeem

[Altera_Forum]

Hello Nadeem! 

 Did you try setting the F Falling edge line to 1 instead of 4?  Also, you said you are using 2 symbols per beat, so that means the clocked video output is 16 bits wide right? 8 for Luma and 8 for chroma. How did you connect it to the ADV7171? It could be possible that the Luma and Chroma are switched and the ADV7171 wouldn't recognize the signal You could also try to use 1 symbol per beat to avoid this problem.  Do you know if the hardware connection between the fpga and the ADV7171 is working?   Regards, Thiago

[Altera_Forum]

hey thiago, thanks alot for your quick reply. 

 Actualy come to think about it , I said the wrong thing.  I have set it to 8 bits, 2 symbols, in sequence and not parallel (hence one symbol per beat i guess ... Is this right).   I initial tried 1, but had no luck.  Well i get an 8 bit out video data, which i connect to my ADV7171( although the adv has option of using 16 bit interface, i have set it up to use only 8 bits.  But I am not sure what to do with the Data Valid signal.DO u leave it unconnected?  I am sure the ADV is connected properly and is set right, as i can enable and disable the in build Test pattern generator, plus when download the SOF file onto my fpga the monitor receives a signal, as from Blue screen(standard no signal color) it turns black and if i increase the brightness i get Vertical green lines.  Do I need a frame buffer before the Video Clocked out IP. Does it make a difference if i set the Test Gen to produce interlaced frames synced on f0 or f1?  I hope u can help me, will greatly appreciate it.  regards nadeem

[Altera_Forum]

Another question I had is that, is it possible that my blanking lines and pixels is wrong?

[Altera_Forum]

Hmm, this is strange 

 I've used this test pattern generator with clocked video output and it worked ok. I loaded the predefined NTSC configuration to ensure the sync signals were correct, and they use F Falling Edge line 1 instead of 4.  It's like the ADV7171 isn't recognizing the signal. Do you know if it has any status registers? The configuration registers are all correct to accept your data? For example, I've seen that it can use or not external sync signals, I don't know if it's expecting them, this must be register configured.  The data valid signal should be always '1' (you could check that with signaltap), so you don't need to worry about it  What are you using as 27MHz clock source?  No, for this test you don't need a frame buffer.  I don't think that the f0 or f1 sync is going to make any difference too. I used f0 in my tests though.  A good thing you could do is signaltap all the outputs and check if they are ok (try to use the predefined NTSC config in the clocked video output). Look for the TRS Symbols, see if they are ok. After that, check the config registers on the ADV7171. If they are also ok and you have an oscilloscope, check if the signals are getting to the ADV7171 pins correctly  I hope this is helpful  Regards Thiago

[Altera_Forum]

Hey Thiago, thanks alot for your help, its now working. It turned out that it was somthing to do with my registers as you suggested. 

 But now oddly enough i am getting the test pattern but it is giving the wrong collors .  it starts with pink light pink purple, black , white, light green, green and dark green.  Any idea why?  thanking you nadeem Jamal

[Altera_Forum]

Nadeem, 

Sounds like you're current problem is a luma/chroma swap to me. This can occur because the luma/chroma are actually swapped from what you expect them to be. I believe Luma is on the lower 8 bits of the clocked video output.  Also  You might find this useful. This is some code I use in one of my projects to define different video standards. Some of the fields of the struct are irrelevant for you but among other things it contains the line numbers for when Vertical and Field flag transitions take place. The horizontal sync is simply the total words minus the active words.  * Statically declare standards */ //3G standards const sdi_standard standard_1080p50 = { 1125, 1920, 2640, 0, 42, 1122, 0, 0, 581, 0, "1080p50", 3, -1, 0, 0, 0, 0, 0, 1125, &sync_out_standard_1080p50}; const sdi_standard standard_1080p59 = { 1125, 1920, 2200, 0, 42, 1122, 0, 0, 699, 0, "1080p59", 3, 0, 0, 0, 0, 0, 0, 1125, &sync_out_standard_1080p59}; const sdi_standard standard_1080p60 = { 1125, 1920, 2200, 0, 42, 1122, 0, 0, 581, 0, "1080p60", 3, 1, 0, 0, 0, 0, 0, 1125, &sync_out_standard_1080p59}; //HD standards const sdi_standard standard_1080i50 = { 1125, 1920, 2640, 564, 21, 561, 584, 1124, 413, 975, "1080i50", 1, -1, 0, 0, 0, 0, 0, 1125, &sync_out_standard_1080i50}; const sdi_standard standard_1080i59 = { 1125, 1920, 2200, 564, 21, 561, 584, 1124, 290, 853, "1080i59", 1, 0, 0, 0, 0, 0, 0, 1125, &sync_out_standard_1080i59}; const sdi_standard standard_1080i60 = { 1125, 1920, 2200, 564, 21, 561, 584, 1124, 290, 853, "1080i60", 1, 1, 0, 0, 0, 0, 0, 1125, &sync_out_standard_1080i59}; const sdi_standard standard_720p50 = { 750, 1280, 1980, 0, 26, 746, 0, 0, 385, 0, "720p50", 1, -1, 0, 0, 0, 0, 0, 750, &sync_out_standard_720p50}; const sdi_standard standard_720p59 = { 750, 1280, 1650, 0, 26, 746, 0, 0, 385, 0, "720p59", 1, 0, 0, 0, 0, 0, 0, 750, &sync_out_standard_720p59}; const sdi_standard standard_720p60 = { 750, 1280, 1650, 0, 26, 746, 0, 0, 385, 0, "720p60", 1, 1, 0, 0, 0, 0, 0, 750, &sync_out_standard_720p59}; //SD standards const sdi_standard standard_480i59 = { 525, 720, 858, 263, 17, 261, 280, 523, 140, 400, "480i59", 0, -1, 1, 9, 269, 272, 6, 522, &sync_out_standard_480i59}; // All line numbers offset by -3 const sdi_standard standard_575i50 = { 625, 720, 864, 313, 23, 311, 336, 624, 164, 474, "575i50", 0, -1, 1, 8, 318, 321, 5, 625, &sync_out_standard_575i50}; // All line numbers offset by -1 //typedef struct{ // int line_count; /**<Number of total lines (vertical res) in standard */ // int active_words; /**<Number of active pixel words in a line */ // int total_words; /**<Number of total words in a line */ // int f_rise; /**<Line number at which F flag is raised (interlaced) */ // int v_fall1; /**<Line number at which V flag is lowered */ // int v_rise1; /**<Line number at which V flag is raised */ // int v_fall2; /**<Line number at which V flag is lowered 2nd time.*/ // int v_rise2; /**<Line number at which V flag is raised 2nd time. */ // int p_change1; /**<Pathological change 1 */ // int p_change2; /**<Pathological change 2 */ // char name; /**<Textual name for this standard */ // int txstd; /**<0=SD,1=HD,3=3G */ // int fastclk; /**<0=148.3516MHz reference clock, 1=148.5MHz reference clock*/ // int edh_enable; /**<0 = No EDH, 1 = EDH */ // int edh_start1; /**<Line number to start EDH caclulation for 1st field*/ // int edh_end1; /**<Line number to end EDH calculation for 1st field.*/ // int edh_start2; /**<Line number to start EDH caclulation for 2nd field*/ // int edh_end2; /**<Line number to end EDH calculation for 2nd field.*/ // int id_ln; /**<Line number to insert TRIO signal ID.*/ // const sync_out_standard *sync_out_std; /**<Struct containing sync_out_standard*/ //} sdi_standard;

[Altera_Forum]

Exactly, the Luma and Chroma must be swapped as suggested by Jakob 

By the way, Jakob, thanks for the code, it will be very useful to me as well  Regards Thiago

[Altera_Forum]

Note to anyone using that code, it assumes the first vertical falling edge occurs at line 0. This is no impact for 3G/HD standards but the line numbers for the SD standards are offset accordingly. 

 Jake

[Altera_Forum]

Ausom thanks to both of you Jkob and thiago, Thanks for the code , is helpfull for sure. 

 Sorry I am not clear on how i could switch my luma and chroma, as i am sending them out with a 8 bit bus in sequence( serially). Only 8 bits are going from my Clocked out IP to video IC chip....  Another side question hope you all don't mind... I have decided to use a SGDMA controller to send data from my SRAM to multiple interfaces , such as    ->Onchip Fifo-> USd Card  SGDMA Controller -> Colorizor-->CSC->Chroma re sampler-> Scaler->Clocked->Video Out.

[Altera_Forum]

Do you think such a structure is feasible.... Can i do without a frame buffer at the end? 

Or will i get a buffer under run? Is there any better way you all can suggest to be able to send a video feed to be able to be shown on a screen and recorded on an sd card at the same time?  I thought before the entrance to each of the interfaces i would put a ONChip Fifo, which would be dual clock hence allowing me to run the system at different clock speeds..   I hope you all dont mind giving me ideas, thanking you nadeem jamal