Stratix II: Input clock from an external PLL

[Altera_Forum]

Hi everyone! 

 I have a problem with my synthesis: I usually use FPGA's internal PLL to drive my RTL, using CLK1.....15p/n to drive the inclk PLL input, but now I need to drive the clock path of my RTL using an external PLL, I have used some of CLK1.....15p/n pins and the special clock buffer for global region but it doesn't work! Any indication? Thanks

[Altera_Forum]

There is no inherent problem with using an external clock source. What exactly is it that doesn't work? 

 If it appears to compile correctly but does not operate as expected, it could be a timing related problem. You must specify the clock settings manually, as Quartus can no longer infer these from the PLL instantiation. Also, IO timings will be affected.

[Altera_Forum]

I already don't understand the clock buffer point. A FPGA global clock tree can be setup by using a dedicated clock input in your design. You don't have to care for clock buffers that are inserted by Quartus automaticly. It doesn't matter, if the clock source is a crystal or some kind of PLL. If there are other problems implied with your design, you apparently failed in clarifying them.