Trouble with state-machine

Altera_Forum · ‎09-25-2008

Hello,

I'm trying to build a state-machine in AHDL using Quartus 2 v7.2. During compilation I get these messages:

Warning (14130): Reduced register "..." with stuck clock port to stuck value GND

Warning (14110): No clock transition on "..." register due to stuck clock or clock enable

Later in compilation, I get this message, telling me that the output of the state-machine is at ground:

Info: Pin AT has GND driving its datain port

Here is a state-machine like I programmed, I must have made some terrible mistakes. Can tell whose?

SUBDESIGN state_machine2

(

s[2..0] : INPUT;

Takt0 : INPUT; %clock%

AT : OUTPUT;

)

VARIABLE

AT : dff;

M1 : MACHINE WITH STATES (zero, one, two);

BEGIN

AT.clk = Takt0;

M1.clk = Takt0;

CASE M1 IS

WHEN zero =>

AT = B"0";

IF (s[] == 1) THEN

M1 = one;

ELSIF (s[] == 2) THEN

M1 = two;

ELSE M1 = zero;

END IF;

WHEN one =>

AT = B"1";

IF (s[]==1) THEN

M1 = one;

ELSIF (s[]==2) THEN

M1 = two;

ELSE M1 = zero;

END IF;

WHEN two =>

AT = B"0";

IF (s[]==1) THEN

M1 = one;

ELSIF (s[]==2) THEN

M1 = two;

ELSE M1 = zero;

END IF;

WHEN others =>

M1 = zero;

END CASE;

END;

Altera_Forum · ‎09-25-2008

I don't see anything obviously wrong with this subdesign.

The errors indicate that one of your registers does not have a valid clock. Clearly, the clock has been connected to both registers in this subdesign. So, is this the top level of your compilation? If not, is it possible that the subdesign is not instantiated correctly from the higher level? Specifically, is it possible that Takt0 is driven by a constant value?

Altera_Forum · ‎09-26-2008

Yes, you're right, the clock wasn't connected to the state machine. Now it doesn't supprise me anymore that it didn't work...

Thank you very much, Philipp