simulation performance

[Altera_Forum]

I'm wondering what's normal performance of the quartus simulations. 

I have a design for Cyclone III that uses about 1900 logic entities and 8 of the dedicated multiplier blocks. It's clocked at 200MHz and I'm simulating 10ms of operation in timing mode. The simulations are taking the best part of an hour to complete on my Dell Latitude D620 laptop with Intel Core2duo T7200. I know not much about the circuit can be told from what I'm describing but is this normal performance? I've noticed that the simulator seems to be single threaded, so only making use of one CPU core. Also, are there any tricks to speed up the simulation? I'm running Quartus II 8.0 web edition license on Windows XP SP2.  When simulating smaller designs before I have often made lots of small changes and re-ran the simulation over and over. When the simulation takes such a long time to complete that's not really an option anymore because the number of changes I can make over the course of my day is very low if I spend most of if waiting for the simulator to finish. :( Is this something I can fix by throwing hardware at it or must I really change my way of doing things in such a way that requires less time spent on the simulator? Currently the design is almost complete but I'm sure there are a lot of bugs in it that I need to fix, right now it looks as if I need to try to break the design into smaller parts for simulation where possible.

[Altera_Forum]

--- Quote Start ---  ... I'm simulating 10ms of operation in timing mode...  When simulating smaller designs before I have often made lots of small changes and re-ran the simulation over and over.  --- Quote End ---     Are you simulating to check the logic functionality? If so, then it should be faster to run functional simulations.  See Rysc's comments about functional versus timing simulation at the end of http://www.alteraforum.com/forum/showthread.php?p=13315.

[Altera_Forum]

You should use a good simulator, the ModelSim SE for example. 

 It takes about 3 min. for me to simulate 50us of a Nios-2 system using Modelsim SE ver. 6.2 (full debug, no optimization)

[Altera_Forum]

Well, it takes 33 minutes to simulate 10ms of my system. That's 2 million clocks at 200MHz.

[Altera_Forum]

--- Quote Start ---  The simulations are taking the best part of an hour to complete on my Dell Latitude D620 laptop with Intel Core2duo T7200. I know not much about the circuit can be told from what I'm describing but is this normal performance? I've noticed that the simulator seems to be single threaded, so only making use of one CPU core.   --- Quote End ---     Yes, this is normal in the sense that QuartusII doesn't make use of multi-threading. I have used QII on quad-core machines and it still operates as a single-thread. If you are using WindowsXP minimize all other windows that you are not using and you can check in the task manager, it drastically reduces cpu usage.

[Altera_Forum]

baldur, did you notice my suggestion to change your simulation mode from timing mode to functional mode? I don't know how much that will help in your case, but functional mode is generally much faster.

[Altera_Forum]

Yeah I noticed that suggestion and for some reason the same simulation takes 1 hour, 6 minutes in functional mode, which baffles the mind because in that simulation mode I don't see the glitches that timing simulation finds in some of the gates.

[Altera_Forum]

It's too bad that the functional simulation wasn't fast enough for you, but the absence of glitches in that simulation mode makes sense. The glitches you see in timing mode are probably dependent on propagation delays through combinational logic. For an edge-sensitive signal like a logic-driven clock (which you shouldn't be using anyway), the glitches would of course be a design concern. For signals in synchronous paths, the glitches don't matter because the slack reported by static timing analysis tells you whether the glitches will settle out in time.

[Altera_Forum]

Hi Baldur 

 A few suggestions (some repeated from previous replies):  1) Try a different simulator - e.g. Modelsim (personally I hate it but hey it's free with the Altera bundle). 2) Try breaking the design down and simulating in pieces 3) Try a more elaborate testbench which includes self checking - i.e. apply stimulus (wait if necessary), check output, if output different to expected report an error - in VHDL this last bit can be done easily with the "assert" command. I'm not sure how this report gets shown in quartus but in modelsim and other dedicated simulators (e.g. ActiveHDL which I love) your message gets displayed in the console.  This last approach has the advantage that you don't have to wade through 10ms of waveforms looking for a fault - the console message tells you when the fault ocurred and you can dive straight in at the right point and have a look.  In VHDL the "assert" function doesn't get synthesised so you can even put this in your RTL code - not just your testbench. You can also mask it off from synthesis with the "translate synthesis_off" and "..._on" pragmas (if you want to).  Half an hour for 10ms worth of 200MHz clock doesn't sound too out of the ordinary (it always depends on the size of your code and clock speed, but I don't think you're an order of magnitude out), so maybe you might benefit from a different approach to simulation.  Personally I do as much self checking in the code and testbench as I can; and I simulate small chunks in detail so that a simulation of the whole design is mainly checking that the interfaces between my chunks are correct - the self checking makes this easier. Self checking and "assert" has the advantage that you can leave a design running and throw random data at it overnight and come morning you just check the console to see if you've had any errors. It takes a bit more time to set up your simulation like this but it pays off over the project.  Hope this helps

[Altera_Forum]

Also... simulating chunks of your design with a testbench for each chunk will enable you to more easily re-use that chunk in another design - you have a piece of RTL and a piece of testbench which can both be ported to another simulation. If you wrap your test code up into one testbench for the whole design then you have to go through a frustrating process of pulling out relevant lines and building another lump of code for your new project.

[Altera_Forum]

I fixed this by throwing more processing power at it. Got a desktop machine with Intel E8500 Core2 duo 3.16GHz and some 800MHz DDR2 running Windows XP. Simulations that took a half hour on my laptop (Dell Latitude D620 with Intel T7200 Core2 duo 2.0GHz) take 10 minutes on the new system. I did also try Modelsim and that is nice and fast for functional simulations but what I really needed were timing simulations. It seems that I'm clocking some parts of the design too fast and in other parts not waiting long enough between feeding input and reading output. None of these problems become apparent in a functional simulation, there everything works ;) 

Only problem is that the web edition license from Altera doesn't allow "terminal server" use so I have to use VNC to control the machine instead of Remote Desktop (I don't have space for another monitor on my workbench so I'm still working on the laptop)

[Altera_Forum]

--- Quote Start ---  I did also try Modelsim and that is nice and fast for functional simulations but what I really needed were timing simulations.  --- Quote End ---    Modelsim can do functional or timing simulations: if you simulate your RTL code then it's a functional simulation; if you simulate the gate-level .vho (VHDL netlist) with sdf timing annotations then you get a timing simulation.  I'm sure there's a Verilog equivalent if you want a gate-level netlist in that language instead.

[Altera_Forum]

Interesting, how do I generate the .vho and the timing annotations that match the device I'm using?

[Altera_Forum]

Assignments >> Settings 

 then EDA Tool Settings >> simulation.  Set up according to what you want.

[Altera_Forum]

--- Quote Start ---  I did also try Modelsim and that is nice and fast for functional simulations but what I really needed were timing simulations. It seems that I'm clocking some parts of the design too fast and in other parts not waiting long enough between feeding input and reading output. None of these problems become apparent in a functional simulation, there everything works  --- Quote End ---     You should catch this kind of problem in static timing analysis if you entered the timing constraints properly. Timing simulation doesn't catch all the problems that static timing analysis does. As I mentioned before, see Rysc's comments about functional versus timing simulation at the end of http://www.alteraforum.com/forum/showthread.php?p=13315.