Cyclone II embedded RAM synthesize away

[Altera_Forum]

I am doing mp3 decoder project using DE2 board and Quartus 8. 

 module decoder ( /* irrelevant declaration */ output FL_CE_N // FLASH Chip Enable ,output wire mem_writedata ); //576 memory interface ( embedded Ram) //wire mem_writedata; wire mem_address; wire mem_data; wire mem_wren; /* irrelevant */ memory_init BKMemory( mem_address, CLK, mem_writedata, mem_wren, mem_data ); endmodule  My problem is that If I comment the Blue and uncomment the red ( that means the same except that mem_writedata is no longer output port ), Quartus will not synthesize my BKMemory block :( . You can see it by looking at the number of LEs in compliation report.  I don't use tri-state becuase I understand that cyclone II have no internal tri-state driver. I have spent several days but still not figure out what is the problem :confused: . Hope that you guys could help me.  PS : the attachment is my project.

[Altera_Forum]

It's not really clear, what you try to achieve, thus my answer may partly miss your problem. 

 Generally, if the output of your RAM isn't connected to the outer world, it will be synthesized away. That shouldn't have any consequences for the design's behaviour, except in simulation of internal nodes. If you want to know the resource requirements of your module, you must connect it up to the top and have any output pins depending on it.  I also don't know, what you're intending with internal threestate drivers. Phsyically, no FPGA of any vendor has internal busses. But you may use them in the RTL and they are translated to multiplexers and point-to-point connections by the HDL compiler, if you find these construct useful to describe your logic. Of course, unequivocal enable conditions for the internal threestate drivers respectively inferred multiplexers must exist.

[Altera_Forum]

TO_BE_DONE

[Altera_Forum]

--- Quote Start ---  mem_writedata is data that will be written to RAM, so it is just input.  --- Quote End ---   I don't know, if the shown code is complete, but an output wire can hardly be the data input to a module. An there are no output ports for data output at all.

[Altera_Forum]

--- Quote Start ---  I don't know, if the shown code is complete, but an output wire can hardly be the data input to a module. An there are no output ports for data output at all.  --- Quote End ---    If possible, please download and check my project. I didn't show all the code because it is too long. Thank you for your effort >:D<

[Altera_Forum]

I took a brief look at the project. I think, mem_writedata is indirectly the only output path depending on the said memory block. So removing this output makes the memory block obsolete. You easily test this assumption by connecting an additional output port from the memory directly.

[Altera_Forum]

--- Quote Start ---  I took a brief look at the project. I think, mem_writedata is indirectly the only output path depending on the said memory block. So removing this output makes the memory block obsolete. You easily test this assumption by connecting an additional output port from the memory directly.  --- Quote End ---    thank for your help, I'll try it :) .

[Altera_Forum]

--- Quote Start ---  I took a brief look at the project. I think, mem_writedata is indirectly the only output path depending on the said memory block. So removing this output makes the memory block obsolete. You easily test this assumption by connecting an additional output port from the memory directly.  --- Quote End ---   thank you very much. I somehow managed to solve the problem

[Altera_Forum]

--- Quote Start ---  I took a brief look at the project. I think, mem_writedata is indirectly the only output path depending on the said memory block. So removing this output makes the memory block obsolete. You easily test this assumption by connecting an additional output port from the memory directly.  --- Quote End ---   thank you very much. I somehow managed to solve the problem