Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16611 Discussions

Error with SOPC generated files

Altera_Forum
Honored Contributor II
1,009 Views

I am using SDRAM controller in SOPC builder, when compiling the project with QuartusII following error appears. 

 

Any help on how to resolve this. 

 

Error: IO_PIN atom "ddr_dqs_to_and_from_the_ddr_sdram_0[0]" has port DQSUPDATEEN that must be connected to the dqsupdate output of a DLL because the dqs_ctrl_latches_enable parameter is set to true 

Error: IO_PIN atom "ddr_dqs_to_and_from_the_ddr_sdram_0[1]" has port DQSUPDATEEN that must be connected to the dqsupdate output of a DLL because the dqs_ctrl_latches_enable parameter is set to true 

 

Thanks a lot, 

Sasi
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
309 Views

I think you get this error because first you have to assign that pins (ddr_dqs_sdram[0] and [1]) as "Use as regular I/O" in Assignements\Settings\Device\Device and Pin Options\Dual Purpose Pins 

 

try it
0 Kudos
Altera_Forum
Honored Contributor II
309 Views

I set all the IO's to "Use as regular I/O" option. It did not solve the problem. 

 

Infact the signals are "ddr_dqs_to_and_from_the_ddr_sdram_0[0]" not there in the top module.  

 

Please let me know if you want me to try anything else. 

 

Thanks.
0 Kudos
Altera_Forum
Honored Contributor II
309 Views

There are two possibilities for this error: 

 

1 - You don't have something connected correctly. Verify that all your DQS pins to/from the DDR2 core are properly connected to top level DQS pins. 

 

2 - Part of your design is being synthesized away because it is not being used. If you've instantiated the DDR2 RAM but you're not actually using it, the logic will be synthesized away and you will get the error shown. 

 

Jake
0 Kudos
Reply