DDR SDRAM controller

[Altera_Forum]

Hi 

 Where can find a complete example design which has sdram controller interfacing custom logic with avalon master...without using nios.    Thanks in advance, usha.

[Altera_Forum]

What is it you're looking for exactly? Are you trying to understand how to write the avalon master? It's pretty simple. You just follow the rules indicated in the specifications document: 

http://www.altera.com/literature/manual/mnl_avalon_spec.pdf  I have several designs which do what you are indicating but I'm afraid they are proprietary. I can answer any questions you have. If you like, you could take a look at the Avalon OpenCores 10/100 Ethernet MAC available in the shared material section of the forum. It has two avalon masters (DMA controllers). They are simple masters (no bursting) and only 32-bits wide.  Jake

[Altera_Forum]

Hi Jake,  

Thanks for the reply.   My requirement is follows…   I have some custom logic (say an adder(16-bit)), and I should read data from ddr-sdram and write back to the ddr-sdram.    My understanding is that the custom logic should have an Avalon mater interface to this. And this ip + ddr-sdram controller + pll to be used in sopc builder to generate the RTL.    I failed to find an example to do this.  Any sample example to do this will be of great help.   usha