Altera PLL and SDC timing constraints for Timequest

[Altera_Forum]

Hi all, 

 is it possible to export SDC scripts from a altPLL megafunction?  I think in most cases it is only necessary to retype all values from the megafunction to the TimeQuest SDC script, so I think this is quiet boring :)  Thanks so far  CYCLONE

[Altera_Forum]

You can use the derive_pll_clocks command to automatically get the TimeQuest settings from the megafunction.

[Altera_Forum]

Not directly from the ALTPLL MegaWizard (although not a bad idea). As Ben pointed out, derive_pll_clocks will provide this for you. You can then use the write_sdc with the -expand option to get the SDC commands into a file: 

 create_timing_netlist derive_pll_clocks update_timing_netlist write_sdc -expand <filename>.sdc

[Altera_Forum]

Also use the -create_base_clocks argument for derive_pll_clocks if you want the clock constraint on the PLL input to be created automatically. 

 As jimbo said, you can use write_sdc to get SDC commands to copy to your own .sdc file, but you can instead copy directly from the messages that derive_pll_clocks produces (omitting the "Info:" from the front of these messages). The messages will be in the .sta.rpt if you compile with derive_pll_clocks in the .sdc file. The messages will be in the Console window if you are working in the TimeQuest GUI; expand the "Info: Deriving PLL Clocks" message to see the submessages you need to copy.  And of course you can just leave derive_pll_clocks permanently in your .sdc file instead of using the create_generated_clock commands if you're willing to use the clock names that derive_pll_clocks produces.

[Altera_Forum]

OK I think that is clear to me :D Thanks so far! 

 I have 2 further questions:  1.) After defining all PLL clock input/outputs I got timing errors after synthesis (setup and hold time violations). Most violations was solved after defining the PLL outputs independend from each other:  e.g. set_false_path -from [get_clocks {can_pll|altpll_component|pll|clk[0]}] -to [get_clocks {can_pll|altpll_component|pll|clk[2]}]  Further more I defined such timings # ************************************************************** # Set Maximum Delay # ************************************************************** # Tco set_max_delay -from [get_registers *] -to [get_pins *] 10 # Tsu set_max_delay -from [get_pins *] -to [get_registers *] 10 # Tpd set_max_delay -from [get_pins *] -to [get_pins *] 10 # ************************************************************** # Set Minimum Delay # ************************************************************** # Th set_min_delay -from [get_pins *] -to [get_registers *] 10  The problem is that I still got hold time errors. And I´m not sure why!? Compiling with physical synthesis does not improve the behaviour.  2.) I still have a lot of unconstrained pathes. How can I get all pathes constrained without typing hundred lines like that:  set_min_delay -from [get_clocks *] -to [get_pins *] 10 set_min_delay -from [get_pins *] -to [get_ports *] 10 set_min_delay -from [get_ports *] -to [get_ports *] 10 set_min_delay -from [get_ports *] -to [get_pins *] 10  I atteached my SDC    Thanks :confused: :( :p   CYCLONE

[Altera_Forum]

Probably too late for Cyclone to care, but in case anyone else sees this thread... 

    --- Quote Start ---  e.g. set_false_path -from [get_clocks {can_pll|altpll_component|pll|clk[0]}] -to [get_clocks {can_pll|altpll_component|pll|clk[2]}]  --- Quote End ---    This set_false_path exception is OK if the design does not require these cross-domain paths to be synchronous, but typically for cross-domain paths the set_clock_groups command is used instead. set_clock_groups cuts all paths in both directions between the clock domains.      --- Quote Start ---  Further more I defined such timings # ************************************************************** # Set Maximum Delay # ************************************************************** # Tco set_max_delay -from [get_registers *] -to [get_pins *] 10 # Tsu set_max_delay -from [get_pins *] -to [get_registers *] 10 # Tpd set_max_delay -from [get_pins *] -to [get_pins *] 10 # ************************************************************** # Set Minimum Delay # ************************************************************** # Th set_min_delay -from [get_pins *] -to [get_registers *] 10  The problem is that I still got hold time errors. And I´m not sure why!? Compiling with physical synthesis does not improve the behaviour.  2.) I still have a lot of unconstrained pathes. How can I get all pathes constrained without typing hundred lines like that:  set_min_delay -from [get_clocks *] -to [get_pins *] 10 set_min_delay -from [get_pins *] -to [get_ports *] 10 set_min_delay -from [get_ports *] -to [get_ports *] 10 set_min_delay -from [get_ports *] -to [get_pins *] 10  --- Quote End ---    You have a mix of get_pins and get_ports. I wonder if you intended all these constraints to be for device pins. For those, you use only get_ports. The get_pins collection is internal points in the design (like a LUT input or a register output), not device pins.      --- Quote Start ---   The problem is that I still got hold time errors. And I´m not sure why!? Compiling with physical synthesis does not improve the behaviour.  --- Quote End ---    I doubt that physical synthesis does anything for hold timing. Make sure you have "Optimize hold timing" enabled in the Fitter Settings. If you have violations on internal paths and if those violations are not from a design problem like an avoidable gated clock, then set "Optimize hold timing" to "All Paths".

[Altera_Forum]

Hi 

 In a simple project,    derive_pll_clocks set sram_clk inst|the_pll|the_pll|altpll_component|pll|clk[2] create_generated_clock -name {sram_clk_pin} -source inst|the_pll|the_pll|altpll_component|pll|clk[2] -offset 0.500 [get_ports {sram_clk}]    set_clock_groups -exclusive -group [get_clocks {inst|the_pll|the_pll|altpll_component|pll|clk[0]}] -group [get_clocks {inst|the_pll|the_pll|altpll_component|pll|clk[2]}]   I got some warning message about unconstrained path. So I have to add the following line to get rid of the warning message.   set_clock_groups -exclusive -group [get_clocks {sram_clk_pin}] -group [get_clocks {inst|the_pll|the_pll|altpll_component|pll|clk[0]}]    The confusing thing is that the TimeQuest should be able to know that any paths related to inst|the_pll|the_pll|altpll_component|pll|clk[2] are independent of inst|the_pll|the_pll|altpll_component|pll|clk[0]}] by setting clock groups the first time. Why should I set clock groups twice?   Many thanks.

[Altera_Forum]

Maybe this reply is too late for bcao, just for anyone else seeing this thread... 

 the creat_generated_clock in the 3rd line is redundant, 'cause derive_pll_clocks already creates all the generated clocks at the PLL outputs for you.    With the creat_generated_clock in the 3rd line, TimeQuest thinks you have another clock called "sram_clk_pin", which is generated from the output clk[2] of PLL, although you specify the source and target as the same. Therefore, you need an additional set_clock_groups to separate it from clk[0].

[Altera_Forum]

hi all, 

I have to connect an asychronous SRAM, the Address to Data valid (read cycle) is 12ns. I want to check the path delay: address_register -> SRAM_ADDRESS pins -> device 12ns tpd -> SRAM_DATA pins -> data_register  will be lower than 20ns (2 cycles of my sys_clk). 1. how I define the output address pind to input data pins delay (12ns of the sram)? 2. how I ask the SDC to check the delay of the path I described?   thanks alot, Eli