It should be relatively straight forward. you will need a clock that is 7X your 28 bit parallel data clock rate, with a 90 degree offset (for some reason they start each new data stream in the middle of the input clock '1' half) . You could use a module with 4 shift registers, an internal altera pll (with phase offset of 90 degrees) with the output clock running 7x the input clock rate. Clock in 7 data bits (on each of the 4 lvds channels), concatenate their output into a 28 bit dcfifo with the 7x clock on the write and whatever data grab rate you wanted on the read side (as long as you ran it fast enough to prevent data overflows).
