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module testmyand;
reg a,b; wire c; initial begin a=0; b=0; # 5 a=1; # 10 b=1; end myand m(a,b,c); endmodule module myand(a, b, c); // Input Port(s) input a,b; // Output Port(s) output c; assign c=a&b; // Additional Module Item(s) endmodule when i want to test the second module using the first module ,Error: Can't synthesize current design -- Top partition does not contain any logic I don't know why?Link Copied
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--- Quote Start --- module testmyand; reg a,b; wire c; initial begin a=0; b=0; # 5 a=1; # 10 b=1; end myand m(a,b,c); endmodule module myand(a, b, c); // Input Port(s) input a,b; // Output Port(s) output c; assign c=a&b; // Additional Module Item(s) endmodule when i want to test the second module using the first module ,Error: Can't synthesize current design -- Top partition does not contain any logic I don't know why? --- Quote End --- First of all you have no input and output ports in your toplevel specified. With no ports in place the Quartus synthesis engine could remove all your logic ( your and-gate). The initial statement and your# value are good for simulation, but could not be used for synthesis. Try this : module testmyand ( a,b,c); input a,b; output c; myand m(a,b,c); endmodule module myand(a, b, c); // Input Port(s) input a,b; // Output Port(s) output c; assign c=a&b; // Additional Module Item(s) endmodule
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