When can i use the "Use shared PLL(s)" option in ALTLVDS

[Altera_Forum]

Hello, 

 i don´t understand how to use the "Use shared PLL(s)" option in the ALTLVDS Megafunction. I use a Cyclone II (EP2C35F484) and wanted to implement an LVDS Transmitter and four LVDS Receivers. The clock frequencys, phase settings, SERDES factors and channels are the same for Receivers and Transmitter. My problem is, that i only have 4 PLLs but i think in total i need 5 PLLs for LVDS and an additional PLL for other purposes. In what circumstances is it possible to share the PLL between the ALTLVDS Megafunctions. I cannot imagine that it is possible to share a pll between a Transmitter, which transmitts its data to an external PCB, and a Receiver which receives data from that external PCB, even if all PLL/ALTLVDS settings and frequencys are the same. The documentation from ALTERA is not very helpful in this point.    Does anybody know how to share PLLs with ALTLVDS Receivers and Transmitters to reduce the number of used PLLs?   I have no idea how to solve the problem without using all the PLLs. It is also not possilbe to change the number of LVDS channels.   If anyone has an idea, it would be very helpful.   Thanks in Advance   Stefan

[Altera_Forum]

Someone else might be able to provide more details, but first off I would throw the megafunctions you want into a design. Quartus II can merge PLLs across blocks, and so I've had it do that without really diving into the details and moved along. If you get a no-fit because there aren't enough PLLs, then dig into it. (And if it does fit, it might be worth looking at the PLLs in the Technology Map Viewer, just to see what feeds what.) 

 Also, when creating the LVDS functions, you have the option to put the PLLs external. This is useful if you want to hand-modify the PLL in some way, like adding another output. This is more painful, and I recommend creating the megafunction with the PLL first, since it's much easier and great when it works, which is most of the time.

[Altera_Forum]

Sharing PLLs is basically possible for LVDS transmitter and receiver using the same reference clock. It doesn't work e. g. for receiver with individual reference clock in source synchronous operation.  

 Normally a LVDS transmitter or receiver (or a group of channels with common clock) needs a slow (frame) clock and fast (bit) clock. Cause a PLL has five outputs, also two different phased LVDS clock pairs can be provided by one PLL. I'm not sure about the options when let the Megawizard automaticly configure shared PLLs, but it would be possible in external PLL mode.