constrain sdram_controller in timequest

[Altera_Forum]

i've never used timequest before. And i want to constrain my design(a sdram_controller) using timequest. i've read quartus handbook and some other documents about timequest(TQ_Analysis_forum.ppt,Constraining SOPC Designs v1.0.doc,etc) but i am still confused about how to add constraints. 

 The design has a clk_in(25MHz),a asynchronous reset_in and a common sdram interface(sd_addr,sd_dq,sd_dqm...)   i generate 2 clocks with a pll from clkin,one to feed my logic(sclk,160MHz),the other to feed sdram(sd_clk,160MHz,phase-shifted)   my sdc file is as below.# ################################# create_clock -period "40.000 ns"   -name {clk_in} {clk_in} derive_pll_clocks set sd_clk sys_pll_inst|altpll_component|pll|clk[2] create_generated_clock   -name sd_clk_pin   -source $sd_clk   [get_ports {sd_clk}] set_input_delay -clock sd_clk_pin   -max [expr 5.5 + 0.6]   [get_ports sd_dq [*]] set_input_delay -clock sd_clk_pin   -min [expr 2.0 + 0.4]   [get_ports sd_dq [*]] set_output_delay -clock sd_clk_pin   -max [expr 1.5 + 0.6]   [get_ports {   sd_cke   sd_cs_n   sd_ras_n   sd_cas_n   sd_we_n   sd_ba [*]   sd_addr [*]   sd_dqm [*]   sd_dq [*]}] set_output_delay -clock sd_clk_pin   -min [expr -1.0 + 0.4]   [get_ports {   sd_cke   sd_cs_n   sd_ras_n   sd_cas_n   sd_we_n   sd_ba [*]   sd_addr [*]   sd_dqm [*]   sd_dq [*]}]# #################################   i am not sure if it is correct. how should i constrain the input_delay and output_delay?which clock should i use?how should i constrain the reset_in?   can someone help me?:confused: :confused:

[Altera_Forum]

It's tough to tell from just this. First, how is sd_clk phase-shifted? From that we'll know the relationship to your non-phase-shifted clock and the default setup and hold requirements.  

 Secondly, when receiving data, is it the roundtrip delay of sd_clk going off chip, clocking data from the sdram, and then it coming back? Just making sure, since this looks like how it's constrained.

[Altera_Forum]

Have you read this thread (http://www.alteraforum.com/forum/showthread.php?t=1269)? There is a good document that explains how to constrain different interfaces with TimeQuest.