Error: top level design entity " " is undefined

[Altera_Forum]

we have problem in compiling VHDL code in Quartus II software. Every time we compile it shows the Error:top level design entity " file name" is undefined. 

 We are even taking care of the case sensitivity.  Our file name, new created project name and entity name in the code are all same.  Plz help us regarding this.

[Altera_Forum]

--- Quote Start ---  we have problem in compiling VHDL code in Quartus II software. Every time we compile it shows the Error:top level design entity " file name" is undefined.  We are even taking care of the case sensitivity.  Our file name, new created project name and entity name in the code are all same.  Plz help us regarding this.  --- Quote End ---    Hi,  did you set the toplevel correctly ? You can check that in Quartus :  Assignments -> Device -> General   Look to the field "Toplevel entity". If this is not your toplevel, write it down here.  Kind regards

[Altera_Forum]

Hi, 

thanks for the reply.. I tried to check the top level entity in the way u said but it is the same name as in program. It is all in small case. Still there is undefined top level entity error.  Should the file name be in small case also?  Is it got to do with the location of the file where it is stored?  Thanks

[Altera_Forum]

Try to avoid the space character in the name, sometimes it has created strange behaviour.

[Altera_Forum]

Hi... 

 Thanks for the reply....  There is no space character in the name. Is there any specific location like 'bin' folder where the files has to be stored while simulating the program?  Please help me with this.. Thanks

[Altera_Forum]

--- Quote Start ---  Hi...  Thanks for the reply....  There is no space character in the name. Is there any specific location like 'bin' folder where the files has to be stored while simulating the program?  Please help me with this.. Thanks  --- Quote End ---    Hi,  you can check whether the file is in the project or not.   Project -> Add/Remove Files in Project  There you can see all the files which are used in the project. If you don't see your top-level files use the "add" button to include the file. Btw: Did you use the Project wizard for setting up your project ?

[Altera_Forum]

The said error message means, that no entity with the said top-level name can be found in any of the design files, the error can clearly be distinguished from file not found.

[Altera_Forum]

--- Quote Start ---  The said error message means, that no entity with the said top-level name can be found in any of the design files, the error can clearly be distinguished from file not found.  --- Quote End ---    Hi FvM,  when the top-level file isn't in the file list, you don't get any message about a missing file.    Did you get a warning like this during Analysis and Elaboration ?  Warning: Can't analyze file -- file C:/altera/quartus80sp1/qdesigns/vhdl_verilog_tutorial/addersubtractor.vhd is missing

[Altera_Forum]

hello, I met with the same question,

[Altera_Forum]

--- Quote Start ---  hello, I met with the same question,  --- Quote End ---     As FvM indicated this error message is caused by the fact that no VHDL entity is found with the name of the "top level entity". It is not enough to name your VHDL file with the name of the top entity. The top entity itself of your VHDL description should have this name.   e.g. In the example below TOP is the "Top Level Entity" and has been declare d like that (see @pletz) file TOP.vhd   entity TOP is port ( ... ); end TOP;    architecture my_design of TOP is begin ... end my_design;

[Altera_Forum]

Hello everybody from rainy southern Germany, 

 I had the same issue, and the tool gives you no sort of description what is wrong, I was missing my HDL file - it was not defined. As posted below, just check under  Project - Add/Remove files in project. If you see no files listed then that is the problem.   By the way, changing the severity of the error messages for HDL input to level 3 did not give me any additional info. This could be improved in my opinion. :confused:    Cheers, Eric

[Altera_Forum]

I encountered exactly the same problem. I verified Assignment->Settings (with my project name)->General/Files/Device and everything looked fine. I also did Project->Add/Remove Files in Project... and everything looked normal. I had a very simple schematic file under the same directory with the project file (directory and project file have the same name). I wanted to try out with the simple one first since do not want to spend time on the complete project before I know it would work. I used the New Project Wizard and went over their tutorial several times. Can anybody explain to me more since I am at dead end. I am new to Altera and this is the free version with Cyclone II. I also tried to call Altera Tech Support but got the recorder taking me around the loop. Thank a bunch. 

SML

[Altera_Forum]

--- Quote Start ---  I encountered exactly the same problem. I verified Assignment->Settings (with my project name)->General/Files/Device and everything looked fine. I also did Project->Add/Remove Files in Project... and everything looked normal. I had a very simple schematic file under the same directory with the project file (directory and project file have the same name). I wanted to try out with the simple one first since do not want to spend time on the complete project before I know it would work. I used the New Project Wizard and went over their tutorial several times. Can anybody explain to me more since I am at dead end. I am new to Altera and this is the free version with Cyclone II. I also tried to call Altera Tech Support but got the recorder taking me around the loop. Thank a bunch. SML  --- Quote End ---    Hi SML,  if your project is a small one, please post the project in the forum. I will have a look to the project.  Kind regards  GPK

[Altera_Forum]

How do I post my project into the forum. GPK please show how. Thank you. 

Regards, SML

[Altera_Forum]

Make a Quartus archive (*.qar file) from the project, go the manage attachments zone when writing a reply.

[Altera_Forum]

I was not able to get any *.qar file. The message I got after archiving was: 

"Project archiving created; however, Analysis Elaboration was not successful. As a result, some files could not be archived". None of the output files complied with the attachment format; therefore I could not upload any files for you to examine. Any ideas please. Regards, SML

[Altera_Forum]

--- Quote Start ---  I was not able to get any *.qar file. The message I got after archiving was: "Project archiving created; however, Analysis Elaboration was not successful. As a result, some files could not be archived". None of the output files complied with the attachment format; therefore I could not upload any files for you to examine. Any ideas please. Regards, SML  --- Quote End ---    Hi,  tricky problem. I think you can only archive a project which successfully fits. If your project is small put the quartus run directory and your source files in a zip file. The Zip file could be attached to the post.  Kind regards  GPK

[Altera_Forum]

Thank you a lot you guys. I sincerely welcome as much help as I can get. Here is the zip file. 

Regards, SML

[Altera_Forum]

I see that your project is set to a top level entity "DramControl", but there's no file with this name. The bdf file apparently intended as top level is "DramCltGen.bdf". It can't work this way. 

 If you open DramCltGen.bdf, you can set it as top level entity in the project menu.  As the next problem, DramCltGen.bdf has illegal pin names containing a "#".  There are additional logic errors and possible problems in the design, e.g. an internal tris-state buffer that is causing an 'U' unknown logic state, when disabled.  P.S. Regarding:  --- Quote Start ---  I was not able to get any *.qar file.  --- Quote End ---   I believe, that you get an error message, but a valid *.qar file has been generated and is contained in your *.zip file anyway.

[Altera_Forum]

Thank a million FvM. 

Regards, SML

[Altera_Forum]

I had the same problem when I first started a while back. The solution I found that allowed Quartus II to compile my Verilog files was: 

 1)File | New | Block Diagram/Schematic File with the same name as Project 2)Click on the HDL source files (*.v etc) (it must be the active window) 3)File | Create/Update | Create Symbol File for Current File 4)Double click on the ProjectName.BDF file you created in Step 1 and insert your new Symbols from you made in step 3 5)Double click on the ProjectName.BDF file you created in Step 1 and insert pin assignments (Inputs, Outputs, etc)  Now Quartus II allowed my verilog modules to compile.  Cheers