Creating delay on an internal signal

[Altera_Forum]

I have an internal signal on a Cyclone II that I need to delay on the order of several nanoseconds. Best practices and omg-he's using-asynchronous-code aside, what would be the best way to do this? Can I use delay components of IO pins? I can't physically connect the pins to make a chain, but I do have plenty of unused pins if I could chain the delays internally. My fallback plan right now is to use LCELLs, but I'd like to hear your input before doing so. 

 I've done this in the past using IOBUFs on Xilinx devices. Is there something similar I could use on the Cyclone II?

[Altera_Forum]

--- Quote Start ---  I have an internal signal on a Cyclone II that I need to delay on the order of several nanoseconds. Best practices and omg-he's using-asynchronous-code aside, what would be the best way to do this? Can I use delay components of IO pins? I can't physically connect the pins to make a chain, but I do have plenty of unused pins if I could chain the delays internally. My fallback plan right now is to use LCELLs, but I'd like to hear your input before doing so.  I've done this in the past using IOBUFs on Xilinx devices. Is there something similar I could use on the Cyclone II?  --- Quote End ---    Why do you need such large delay for the internal signal ?

[Altera_Forum]

Hi, 

 I have used io delay successfully in a design. I am not sure of how much delay was involved but was enough for my phase comparator(for two external clocks). I connected the target delay signal to io and back to phase comparator.   you can also use a cascade of lcells.   kaz

[Altera_Forum]

Forum member Rysc has demonstrated, how to set delay by timing constraints: 

http://www.alteraforum.com/forum/showthread.php?t=3068 A delay can also generated manually by inserting logic-cells with a keep attribute. With Cyclone III, 4 to 5 logic cells insert 1 ns delay.

[Altera_Forum]

--- Quote Start ---  Forum member Rysc has demonstrated, how to set delay by timing constraints: http://www.alteraforum.com/forum/showthread.php?t=3068 A delay can also generated manually by inserting logic-cells with a keep attribute. With Cyclone III, 4 to 5 logic cells insert 1 ns delay.  --- Quote End ---    Fine, but how do I do that if I don't need to bring it out to a pin? I have mostly worked with Xilinx parts in the past, and I have been able to chain IBUFs and OBUFs via internal signals to create delay. Yes, in this case those pins become active, but serve no actual purpose in the design.  Can I assign a constraint between two internal nets and let the router create the delay? That seems to have been the solution in the thread you referenced, but they were applying constraints to pins. I have extra pin locations that I can throw at this problem, but cannot physically make external connections to them.

[Altera_Forum]

A simple, parameterizable logic cell delay line example goes like this: 

 signal delay_line: std_logic_vector(DELAY-1 downto 0); attribute keep: boolean; attribute keep of delay_line: signal is true; begin gen_delay: for i IN 1 TO DELAY-1 generate delay_line(i) <= delay_line(i-1); end generate; delay_line(0) <= inp; outp <= delay_line(DELAY-1); As discussed in another thread, the method doesn't work with CPLD (apart from MAX II, that is an embedded flash FPGA).

[Altera_Forum]

That looks like a much easier solution than I was expect. I'll give it a try :) 

 Is there a way to view this specific path in the Timing Analyzer, or do I need to bring the signals out to testpoints and manually measure it to determine the delay?

[Altera_Forum]

Quartus simulator can be also expected to show the real timing.

[Altera_Forum]

--- Quote Start ---  A simple, parameterizable logic cell delay line example goes like this:   signal delay_line: std_logic_vector(DELAY-1 downto 0); attribute keep: boolean; attribute keep of delay_line: signal is true; begin gen_delay: for i IN 1 TO DELAY-1 generate delay_line(i) <= delay_line(i-1); end generate; delay_line(0) <= inp; outp <= delay_line(DELAY-1); As discussed in another thread, the method doesn't work with CPLD (apart from MAX II, that is an embedded flash FPGA).  --- Quote End ---         Hi,   But i can run this code on EPM7512AEQC144-12, the tool version is 9.1+sp1. Why?

[Altera_Forum]

What's the mean of "doesn't work with CPLD "?