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Quartus - Asynchronous RAM

Altera_Forum
Honored Contributor II
‎12-10-2008 05:22 PM
1,647 Views

Hi!!!! 

Is it possible to implement asynchronous RAM in VHDL for the Stratix II device?  

If it is possible, how can I do?  

 

I need your help... is very important for me because ,I'm working with this device in my final career proyect...  

Thx for your help!!!  

Mary
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Altera_Forum
Honored Contributor II
‎12-10-2008 05:28 PM
858 Views

I'm working with the megafunction altsyncram,  

Should I change some parameters to the memory that is generated? 

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Altera_Forum
Honored Contributor II
‎12-10-2008 05:35 PM
858 Views

Also,how I must work with the Pseudo-Asynchronous Modes??? 

Thx for your help!!!!
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Altera_Forum
Honored Contributor II
‎11-30-2011 06:47 AM
858 Views

hi  

i need an asynchronous RAM ?  

i cant find one with no clk port!  

plz help me  

thanks in advance.
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Altera_Forum
Honored Contributor II
‎11-30-2011 07:55 AM
858 Views

What FPGA are you targetting? Most current FPGA only have synchronous RAMs.

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