Not operational : clock skew > data delay

[Altera_Forum]

I'm currrently doing a project on emulating a CPU functions. i've integrated various blocks of the CPU and during the compilation I received this warning:  

 Warning: Circuit may not operate. Detected 201 non-operational path(s) clocked by clock "clock" with clock skew larger than data delay. See Compilation Report for details.   where does this warning comes from? and how can i overcome this problem?

[Altera_Forum]

Hi, 

 One possible reason is that your clock is gated. If you have a gated clock you will need to avoid it from the start or else connect it to the global lines.   kaz

[Altera_Forum]

kaz, 

 what do you mean by gated clock? i'm using if clk'event and clk= '1' then... to detect the clock signal. in each clock signal will transit to another new state. furthermore, what is global lines? i'm sorry i'm really i newbie in vhdl

[Altera_Forum]

Hi, 

 A clock source to fpga is either external and connected to fpga clock pin(This is global line) or a clock signal is generated internally by two methods: 1) PLL (again this becomes global) 2) from logic e.g. inversion or halving by flipflops or using counters...etc. Here Quartus wouldn't make it global always so you need to to go to: assignment editor, select the clock signal and choose global.   kaz

[Altera_Forum]

furthermore, what does this mean by "Specify derived clock settings for all nodes functioning as derived clocks in the design"?

[Altera_Forum]

Hi, 

 Quartus classifies clocks as: Base or derived. Base clock is the one connected to input clock pin. Derived clocks are those generated from a base clock in a PLL or logic(gated). for PLL derived clocks quartus generates clock settings.   For base or gated derived clock you need to enter the clock settings e.g. frequency so that timing analyser can give you correct results.   But first make your clock global then enter settings in the timing analyser.   kaz