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VHDL User Library

Altera_Forum
Honored Contributor II
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Hello : 

 

I am in the process of migrating my designs from schematic to VHDL, 

and have hit a snag with creating a company library of components. I would 

greatly appreciate any help. 

 

I have a number of components that I want to be available for all my 

projects. As an example, UnsignedDivide implemented in UnsignedDivide.vhd 

with an entity of 

 

ENTITY UnsignedDivide IS 

GENERIC ( NW : POSITIVE := 32 ; -- Numerator Width 

DW : POSITIVE := 16 ; -- Denominator Width 

QW : POSITIVE := 16 ); -- Quotient Width 

PORT (Clk : IN STD_LOGIC ; 

Start : IN STD_LOGIC ; 

Num : IN UNSIGNED (NW-1 DOWNTO 0) ; 

Den : IN UNSIGNED (DW-1 DOWNTO 0) ; 

Done : OUT STD_LOGIC ; 

Quo : OUT UNSIGNED (QW-1 DOWNTO 0) ); 

END ENTITY UnsignedDivide ; 

 

If I include this file in my project, I can directly instantiate multiple 

dividers and they all work fine. 

 

But I want to put all such files in a library and not have to include them 

in each project source.  

 

This was easy in schematic designs - just add a directory as a library that contained all the BSF, BDF and megawizard generated VHD files and they could just be added to any BDF in my project. i.e. the library was purely source. 

 

So I need to use a package I think. 

 

So, I created MyCompanyLibrary.vhd that contains : 

 

PACKAGE MyCompanyLibrary IS 

COMPONENT UnsignedDivide IS 

GENERIC ( NW : POSITIVE := 32 ; -- Numerator Width 

DW : POSITIVE := 16 ; -- Denominator Width 

QW : POSITIVE := 16 ); -- Quotient Width 

PORT (Clk : IN STD_LOGIC ; 

Start : IN STD_LOGIC ; 

Num : IN UNSIGNED (NW-1 DOWNTO 0) ; 

Den : IN UNSIGNED (DW-1 DOWNTO 0) ; 

Done : OUT STD_LOGIC ; 

Quo : OUT UNSIGNED (QW-1 DOWNTO 0) ); 

END COMPONENT UnsignedDivide ; 

-- etc 

END PACKAGE MyCompanyLibrary ; 

 

I cannot find how to progress from here. 

 

I am hoping to do something like this at the top of all my VHD project files 

 

LIBRARY IEEE ; 

USE IEEE.STD_LOGIC_1164.ALL ; 

USE IEEE.NUMERIC_STD.ALL ; 

 

LIBRARY MYLIB ; 

USE MYLIB.MyCompanyLibrary.ALL 

 

I can make this work in ModelSim by mapping a library MYLIB in my project, 

and pre-compiling all the VHD of my library (the pkg file and the 

entity/architecture files) into this. 

 

I have been searching the Quartus help for hours now and can't find what I'm looking for. 

 

Any help will be appreciated. 

 

Thanks 

Gary
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Altera_Forum
Honored Contributor II
565 Views

Your library gets compiled into 'work' by default with quartus. There may be a way to link certain files into a library but it's really just semantics by that point. 

 

library work ; use work.mycompanylib.unsigneddivide ;Alternatively, you can use 'all' or if you didn't really care about the component, you could instantiate the entity directly: 

 

U_unsigned_divide : entity work.unsigneddivide(archname) port map ( ... ) ;Does this help out?
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Altera_Forum
Honored Contributor II
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Thanks for your help.  

 

Doing as you suggest still seems to require me adding unsigneddivide.vhd (or the vhdl file containing the PACKAGE declaration) as a PROJECT source file.  

 

If I explicitly add these files, then other files that directly instance unsigneddivide, or instance the component, compile OK.  

 

If I delete the files from the project I get "Error (10481): VHDL Use Clause error at TopLevel_TwoDividers.vhd(73): design library "work" does not contain primary unit "olvUnsignedDivide", even though the directory that contains the source file is specified as a project library. 

 

This is what I am trying to achieve, specifiying a library that contains all my pre-written and debugged library stuff, without having to add each source file to the project I'm working on.  

 

This works fine when synthesizing a schematic design, the compilation process finds the necessary design files in the specified library directories. It even works fine if I have a parameterized symbol in my schematic called unsigneddivide.bsf - the compilation process finds the VHD file in the specified library and there are no problems. 

 

My apologies if these are dumb questions, I wrote my first line of VHDL this week.
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Altera_Forum
Honored Contributor II
565 Views

Not dumb questions at all, but I wonder if it's a good design practice to have source files that you rely on not be in the scope of the project? Is there a reason you don't want to explicitly add the files to your project? Do you feel they clutter up your project, or are you just used to not having to specify this?

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Altera_Forum
Honored Contributor II
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Yes, clutter is my concern. Comparing with SW development, it's like I don't want to have the source for "sprintf" to be part of my project, I just want to include stdio.h.  

 

It seems that if I include a single VHD file from my library "MyLibPackage.vhd" that contains package MyLib which includes all the component declarations, then use WORK.MyLib.All, compilation will then find the instantiated components in the corresponding VHD files in the library, issuing a warning. 

 

I think this is the approach I will take as I start to implement more VHDL source. 

 

Thanks for your help
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Altera_Forum
Honored Contributor II
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Altera usually adds library pathes to the project, when importing e.g. IP cores and stores the sources in separate directories. But they prefer to explicitely include the design files to the project. Using implicite import (by entity name), you get a danger of mixing up different file versions, I fear.

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Altera_Forum
Honored Contributor II
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In the Settings dialogue box, click the "Libraries" Category on the left and you can add global or project specific libraries. 

 

If memory serves me correctly then there was a bug with one of them but I can't remember which one. 

 

Have a play and see what works.
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