DE2 SRAM Flash & Tristate Bridges

[Altera_Forum]

Hi, 

in the example DE2 designs for NIOSII SOPC systems, the SRAM is connected directly to the Avalon Bus while the Flash is connected via a tristate bridge. What is the reason for that?  In the Quartus Handbook it says that one has to implement a tristate bridge if the offchip component has bidirectional pins. That is the case for both memories. Address & databus sharing is not designed into the board, the busses are separate, so no tristate bridges for that either. :confused: Can someone elude me? Thx, Fried

[Altera_Forum]

Hi, 

 what do you mean address/data bus sharing? not clear. My understanding is that if avalon IF data(as opposed to fpga pins) is bidirectional then you need tristate bridge. I don't know about DE2 but I will assume avalon data is bidirectional for flash but separate input/output for sram(then bidirectional at fpga pins through your tristate bridge).

[Altera_Forum]

SRAM and Flash are connected by separate individual address and data busses to the FPGA. Both data busses are bidirectional, SRAM is 16 bit and Flash is 8 bit.

[Altera_Forum]

I understand address and data are separate. I also understand that data in both cases are bidirectional. But is the avalon interface itself having bidirectional data ports in both cases?

[Altera_Forum]

I think so, both connections in SOPC builder go directly to the cpu intsruktion and data masters, so I don't see how these path can be unidirectional? Well, I'll try to build a system without the tristate bridge to the flash and see if it will work. I have yet to acquire a good understanding of bridges and their use. 

Thx, Fried

[Altera_Forum]

So who is doing the tristate work? It must be either the Nios system or somewhere in the fpga. Else it can't be done. 

 For any bidirectional pin you must have a tristate arrangement to cutoff your output drive when reading the input. Sopc does it for you plus some extras e.g. address mode transfers.