Stratix III Fast PLL I/O issue

Altera_Forum · ‎12-18-2008

Hi there,

I'm currently developing a design for a Stratix III using the altlvds receiver and transmitter with internal, shared PLLs. Synthesis in Quartus 8.1 works fine but the fitter throws this error (iClk50MHz is the slow symbol clock feeding the Rx and Tx PLLs):

Error: Pin iClk50MHz driving clock input pin of fast PLL WrapHSSRintPLL:unitReceiver|HSSRintPLL:unitHSSRintPLL|altlvds_rx:altlvds_rx_component|HSSRintPLL_lvds_rx:auto_generated|pll cannot have I/O standard 1.8 V

This clock input on the Altera Stratix III DSP Development Board Rev C is single ended and the bank is supplied with 1.8V. Changing the I/O standard for this clock input to LVDS removes this fitter error but I must use this clock input on this board.

Any suggestions how to tell Quartus to use single ended clock inputs for designs with the altlvds core?

thanks in advance,

lestard

Altera_Forum · ‎12-18-2008

The problem seems to be solved by adding one additional clk buffer (altclkctrl from megawizard) between the input clock and all other units.

lestard