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I need to generate a 124M pulse from a 52M pulse. Restrited by the pipeline stages, I use this method:
always @ ( ... posedge clk_124 ) ... sig124 <= P52; end always @ ( ... posedge clk_124 ) ... p124 <= P52 & (~P124); end I wonder if this method is safe? :DLink Copied
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--- Quote Start --- I need to generate a 124M pulse from a 52M pulse. Restrited by the pipeline stages, I use this method: always @ ( ... posedge clk_124 ) ... sig124 <= P52; end always @ ( ... posedge clk_124 ) ... p124 <= P52 & (~P124); end I wonder if this method is safe? :D --- Quote End --- Hi, what is the purpose of sig124? Should be "p124" the same signal as "P124" ?Be aware that verilog is case sensitive.
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--- Quote Start --- always @ ( ... posedge clk_124 ) ... sig124 <= P52; end always @ ( ... posedge clk_124 ) ... p124 <= P52 & (~P124); end --- Quote End --- Shoudn't the second process be always @ ( ... posedge clk_124 ) ... P124 <= P52 & (~sig124 ); end i.e. you are generating a pulse of 1 clk_124 period when P52 is ''1' and the last value of P52 ( Stored in sig124 FlipFlop) is 0, in effect a rising edge detector. Otherwise it should be "safe" assuming P52 is synchronous to clk_124. If it isn't you will need to add extra pipeline flipflops to reduce the effects of metastability in clock domain crossing i.e always @ ( ... posedge clk_124 ) ... sig124_L1 <= P52; sig124_L2 <= sig124_L1; sig124_L3 <= sig124_L2; end always @ ( ... posedge clk_124 ) ... p124 <= sig124_L2 & (~sig124_L3); end
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