FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
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DSP Development Kit, Stratix II Ed

Altera_Forum
Honored Contributor II
‎12-23-2008 10:05 AM
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Normally, design file download is well working.. but, sometimes the development kit initialized after downloading.... I think it is totally doesn’t make sense...what is probably cause this
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Altera_Forum
Honored Contributor II
‎12-23-2008 07:18 PM
339 Views

i have also noticed this behavior. i will let you know if i figure out the issue.

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Altera_Forum
Honored Contributor II
‎12-23-2008 11:26 PM
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ok tempeku i have solved my issue, hopefully this will solve yours too. 

 

in Quartus goto Assignments -> Settings -> Device 

click Device and Pin Options 

click the Unused Pins tab 

change the reserve all unused pins field to "As input tri-stated with weak pull-up resistor" 

 

my unused pins were set to drive ground by default which caused the fpga to read the configuation prom about half the time. now it reads my sof 100% of the time.
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