Hi,
I am doing a project with Quratus 8.1 (with SP1, if matters), and I'm trying to simulate one of my design files (VHDL) with the Quartus internal simulator. So I added only the pins in that specific design file (in the node finder's filter I chose "design entry(all names)", created the waveform, chose functional, created a netlist, and started simulation).
The problem is, the simulator (in the simulation report window) shows only the output pins of the entire project, and not of that specific design file (or instance). Of course I can select the option of not adding the output pins automatically, but then I wouldn't see anything. What I actually want to simulate are the output pins and signals of that specific design file, and not of the entire project. How do I do this?
Thank you
