Legacy DDR compilation error

[Altera_Forum]

Hi, 

in a project I have been working on for a while this message suddenly appeared:  Warning: Atom "DDR1:DDR1_ddr_sdram|DDR1_auk_ddr_sdram:DDR1_auk_ddr_sdram_inst|DDR1_auk_ddr_datapath:ddr_io|DDR1_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_captured_rising[0]" has port DDIOREGOUT that should be connected in DDIO input and bidirectional modes Warning: Atom "DDR1:DDR1_ddr_sdram|DDR1_auk_ddr_sdram:DDR1_auk_ddr_sdram_inst|DDR1_auk_ddr_datapath:ddr_io|DDR1_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_captured_falling[0]" has port REGOUT that should be connected in DDIO input and bidirectional modes Warning: Atom "DDR1:DDR1_ddr_sdram|DDR1_auk_ddr_sdram:DDR1_auk_ddr_sdram_inst|DDR1_auk_ddr_datapath:ddr_io|DDR1_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_captured_rising[1]" has port DDIOREGOUT that should be connected in DDIO input and bidirectional modes Warning: Atom "DDR1:DDR1_ddr_sdram|DDR1_auk_ddr_sdram:DDR1_auk_ddr_sdram_inst|DDR1_auk_ddr_datapath:ddr_io|DDR1_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_captured_falling[1]" has port REGOUT that should be connected in DDIO input and bidirectional modes  and so on.. for every IO register for this particular instance. I have one more.  And that probably cause the following error in timing verification: Critical Warning: Could not find 'wdata_r' or 'resynched_data' registers needed to check PLL offsets. Will continue assuming resynch PLL is set to 303 Error: Cannot find destination node 'DDR1:DDR1_ddr_sdram|DDR1_auk_ddr_sdram:DDR1_auk_ddr_sdram_inst|DDR1_auk_ddr_datapath:ddr_io|DDR1_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|\g_dq_io:0:dq_io~ddio_out_reg  Has anyone seen this? I have recompiled the core, using 8.1.  apus

[Altera_Forum]

This is most likely because the registers on the DDR read path have been optimised away. 

 You should be able to see messages to this effect in the synthesis report. One quick way to stop them getting optimised away is to wire all the local_data bits to a (virtual) pin via a big or gate.

[Altera_Forum]

Hi, 

I just found the error: The requirements for when to use external resynch clock must have changed from ver 8.0 to 8.1. So the ddr compiler automatically adds a resynch clock when you recompile the core. (In my case) The BIG PROBLEM is that quartus does not flag the fact that the resynch clock is unconnected, it just compiles the project.  The next issue is the fact that the scripts that the timing analyzer sets up cannot figure out that the resynch clock from the pll is delayed properly (303 deg). So it flags an timing error. I have to add that I have checked the reports in the fitter section, and the delay is properly reported, so I am not sure what do to at this point.  Solution? Stick to version 8.0 of the legacy ddr core. I have not reported this issue to altera.  apus

[Altera_Forum]

It should be possible to disable the dedicated resync clock by going to the 'Advanced' tab and manually overided the resync phase selection. 

 The message "Critical Warning: Could not find 'wdata_r' or 'resynched_data' registers needed to check PLL offsets. Will continue assuming resynch PLL is set to 303" means that the script couldn't find one or both of those registers in the post-fit netlist, which is suggests that they are being optimised away. If the timing analysis completes sucessfully anyway, then everything should be fine as long as the dedicated resync clock has not been changed from the value that the megawizard calculated. Most likely a register the timing script can't do without has been optimised away too, and it will fail later on. 

[Altera_Forum]

Hi, 

by tuning the distances from the ddr to the fpga i was able to use the write clock as resynch clock. (In ver 8.1) I had a couple of ps to work with.