Write to SRAM in vhdl; Then read into NIOS?

[Altera_Forum]

I would like to write data to a specific SRAM address using verilog (no nios) and then access that same memory address using the NIOS processor. 

The main purpose for this is to execute a video processing algorithm in hardware, and then have the results posted into memory for access by the soft processor for main program execution. (Think vision system).   Is this possible? How would it be best to synchronise my writes in hardware versus my reads in NIOS? Perhaps a shifting memory address such that I am reading from a different address than writing?   I am using a DE2-70 board which I believe has multiple external SRAM chips. I would be glad for any pointers you can give.   Thanks.

[Altera_Forum]

The easiest way would be I think to design your own SOPC component, with an Avalon Master interface. Thus the component will be able to write to the memory, and the SOPC builder will automatically add some arbitrators to share the memory accesses between your component and the NIOS CPU. 

Using a DMA component is another solution, depending on how you want to access the memory.

[Altera_Forum]

--- Quote Start ---  The easiest way would be I think to design your own SOPC component, with an Avalon Master interface. Thus the component will be able to write to the memory, and the SOPC builder will automatically add some arbitrators to share the memory accesses between your component and the NIOS CPU. Using a DMA component is another solution, depending on how you want to access the memory.  --- Quote End ---     Unfortunately I have limited experience creating SOPC components. Do you know of any documentation or (preferably) examples to help me on my way?

[Altera_Forum]

I have implemented something like this - however i am using the 3c120 board  

with more resources, but the concept is same.  Like Daixiwen said, you can use Altera SGDMA, to bring the data into your sram. You need to write a custom verilog module which will provide an interface between your incoming video data and the Avalon streaming port of the SGDMA.  Assuming it is image processing done in software - i think you do not require 30fps ? then you can setup the SGDMA to deposit data to your sram buffer address and generate an interrupt when its done.  You can control the frame capture this way by enable/disabling your custom module.  Setting proper arbitration values and depending on your software you can get a higher frame rate.  Regards Foram

[Altera_Forum]

The Avalon specification can be found here (you'll find both the Avalon Memory Mapped interfaces to make a SOPC component, and the Avalon Stream interface if you plan to use the SGDMA component instead) : http://www.altera.com/literature/manual/mnl_avalon_spec.pdf?gsa_pos=3&wt.oss_r=1&wt.oss=avalon 

Altera also made a template of a Avalon Memory Mapped Master, that you can find here: http://www.altera.com/support/examples/nios2/exm-avalon-mm.html?gsa_pos=1&wt.oss_r=1&wt.oss=avalon%20template