SoPC - VHDL questions

[Altera_Forum]

Hi, 

 I ran into a couple of questions: I'm building a new component for the SOPC. It generated a template that seems to me not 'generic' VHDL   entity pio_TERAchip_data is   port (  -- inputs:  signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);  signal clk : IN STD_LOGIC;  signal in_port : IN STD_LOGIC_VECTOR (31 DOWNTO 0);  signal reset_n : IN STD_LOGIC;   -- outputs:  signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)  ); end entity pio_TERAchip_data;  -> Here I haven't seen declaring a signal in a port (like in signal clk : in std_logic;) Is this the same as: "clk : in std_logic;"?   2nd question concerns and odd construction (I guess it's a casting, but I'm not sure)   readdata <= std_logic_vector'("00000000000000000000000000000000");   Why this " ' " behind the std_logic_vector? And why this rather diffucult construction?   wasn't it easier to write: readdata <= (others => '0'); ?   Thanks in advance, Luc

[Altera_Forum]

Good questions! 

 The word "signal" in the entity is used to distinguish the port as a signal rather than say a file. It is assumed to be a signal if omitted, which in 99% of cases that I have seen it usually is!  http://tams-www.informatik.uni-hamburg.de/vhdl/tools/grammar/vhdl93-bnf.html#concurrent_assertion_statement  Has a great VHDL syntax browser.   As to the type cast attribute question, I have no idea why the template is coded as shown and I agree that your suggested way is much neater. :confused:   Maybe this is something to do with the rules used by the tool-set to automate code generation.  I would be tempted to modify the template to suit your coding style.

[Altera_Forum]

Do you mean I could 'probably' alter the code to the simpler version or should I leave as is. 

Unfortunately it's not easy to read ....   Luc

[Altera_Forum]

I have seen an explanation of the std_logic_vector' thing before as sometimes you see string'("tally ho"). I can't find the explanation I came across but basically it is to explicitly specify the type of your literal e.g. "0000000" could be std_logic_vector or a string. Here obviously there is no doubt as to what type you want but if for example you had some function which was overloaded for string and std_logic_vector then you may need to ensure one or the other was called when you passed in your literal. 

 Bit of a vague explanation and sorry I can't find the proper reference for you. Basically I wouldn't worry about it and follow vernmid's advice instead.  Is this template something that will get frequently updated? If you have automatically generated code from say a state machine editor that gets updated every time you make a change to the state diagram then I'd leave it as it is. If it's just a starting point and you are going to manually maintain the file as you would any other VHDL file then change it so it makes sense to you. (others => '0') is like you suggest a much more generic and maintainable way of writing it.

[Altera_Forum]

I have a related problem. 

A line from a test bench generated by the SOPC builder:  active_and_waiting_last_time <= std_logic'('0');  Ncsim doesn't like this. Here is the warning message:  "white space assumed after apostrophe [13.5]"  The same construct for std_logic_vector is accepted: No warning or error for this line:  address_from_the_master_0_last_time <= std_logic_vector'("00000000000000000000000000000000");  Can anyone explain this? I don't like warnings that I don't understand.

[Altera_Forum]

What's your intention to use a qualified expression in this place? It seems meaningless here.

[Altera_Forum]

--- Quote Start ---  What's your intention to use a qualified expression in this place? It seems meaningless here.  --- Quote End ---  As I mentioned, the code is generated by Altera tools. There are many meaningless qualified expressions in the code, but ncsim only complains for "std_logic'('0')" and "std_logic'('1')".  It seems to be legal VHDL code, so I don't understand the warning from Ncsim.

[Altera_Forum]

No warning from modelsim 

Raise an issue with incisive?