Error 10500

Altera_Forum · ‎02-14-2009

LIBRARY ieee; -- Octal decoder using Boolean equations--

USE ieee.std_logic_1164.ALL;

ENTITY decoder_a IS

PORT(a0,a1,a2 : IN std_logic;

y0,y1,y2,y3,y4,y5,y6,y7 : OUT std_logic;

END decoder_a ;

ARCHITECTURE arc OF decoder_a IS

BEGIN

y0 <= (NOT a2) AND (NOT a1) AND (NOT a0);

y1 <= (NOT a2) AND (NOT a1) AND ( a0);

y2 <= (NOT a2) AND ( a1) AND (NOT a0);

y3 <= (NOT a2) AND ( a1) AND ( a0);

y4 <= ( a2) AND (NOT a1) AND (NOT a0);

y5 <= ( a2) AND (NOT a1) AND ( a0);

y6 <= ( a2) AND ( a1) AND (NOT a0);

y7 <= ( a2) AND ( a1) AND ( a0);

END arc;

I insert this code, and it comes up with this:

Error (10500): VHDL syntax error at lab43.vhd(7) near text "END"; expecting an identifier ("end" is a reserved keyword), or "constant", or "file", or "signal", or "variable"

Any ideas on how to fix it? I'm sorry if it's something blatantly obvious that I'm missing, but I've gone over it for the past couple of hours and can't figure it out. :confused:

Altera_Forum · ‎02-14-2009

You are missing the closing parenthesis in the entity port list.

Altera_Forum · ‎01-09-2010

Hello,

this my 1st project involve vhdl.this project,my supervisor wants me to use up3 board,receive 8 bit data from ADC, process it and display through visual basic(PC)..

this what i got so far..if the problems is too obvious,im still amateur bro..

1. i got error 10500 a lot

2. how to communicate up3 board using serial,did it still need vhdl code?

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity up3_board is

port( datain_adc: IN STD_LOGIC_VECTOR(7 downto 0);

clock: IN STD_LOGIC; -- Clock Input from Altera Board

dataout_serial: OUT STD_LOGIC_VECTOR(7 downto 0));

end up3_board;

architecture BEHAVIOR of up3_board is

IF RISING_EDGE(clock) THEN

PROCESS(clock,datain_adc)

BEGIN

if datain_adc='00000000'--data from ADC,not correct yet..

then

dataout_serial<="00000000";--serial output in binary..not correct yet

elsif datain_adc='00000001'

then

dataout_serial<="00010000";

elsif datain_adc='00000010'

then

dataout_serial<="00010101";

elsif datain_adc='00000011'

then

dataout_serial<="00010110";

elsif datain_adc='00000100'

then

dataout_serial<="00010111";

elsif datain_adc='00000101'

then

dataout_serial<="00011000";

elsif datain_adc='00000110'

then

dataout_serial<="00011001";

elsif datain_adc='00000111'

then

dataout_serial<="00011010";

elsif datain_adc='00001000'

then

dataout_serial<="00011010";

elsif datain_adc='00001001'

then

dataout_serial<="00011010";

elsif datain_adc='00001010'

then

dataout_serial<="00011010";

elsif datain_adc='00001011'

then

dataout_serial<="00011010";

end process;

end BEHAVIOR;

Altera_Forum · ‎01-11-2010

3 problems I can see:

1. you forgot an "end if"

2. Id recommend you have an else case, otherwise you'll create latches.

3. You have "clock" in the sensitivity list, but you havent used the clock at all in the process, so it is NOT a syncronous process.

Altera_Forum · ‎01-12-2010

thanks...:)