Functional Simulation is Correct,But Timing is Incorrect

[Altera_Forum]

Hi,I wrote an LDPC Encoder, It's Functional Simulation is Correct, But When I use Timing Simulation , The data read from ROM is Incorrect , I can't find where the problem is , Please help me , Thank you!

[Altera_Forum]

It is rather difficult to say where you have gone from the very limited information you have posted. 

 Yet here are some guidelines 1. Timing simulation is wrong means some part of your code with clock tick events has a mismatch somewhere.  It is a good practice to start with reset and intialize everything   2. Your .vwf should give you an idea where it is going wrong. Stretch your time bar to get a clear idea of waveforms.Comparing the .vwf files of functional and timing simulation might give an idea.   3. In timing simulation, for the first clock cycle data may not change.   4. If you have written lot of loops within a process ,it will be a good idea to check it.   5.check the warnings given by QUARTUSII. If you find anything suspicious ,then right click and get the help for it

[Altera_Forum]

srf6791 (http://www.alteraforum.com/forum/member.php?u=11003): 

 Thanks for your answer. I checked my design with your guideline 1 , and I found a problem: the posedge of clk near the change edge of the address of the ROM , so I add an inverter between the clk to the ROM ， OK ， the data became correct.  Thank you again~

[Altera_Forum]

Hi, alterwoord... I'm sorry, I try to simulate a simple wimedia LDPC coder-encoder chain.. I give all requested signals (Clk,Reset,in_valid,start and end of packet pulses, etc) to the encoder but the outputs remains in absolute undefined status on all the signals.. do you meet similar issue when you simulate? (quartus+modelsim, no errors) . )'m perform a simulation with a 100 mhz pll clk.. conder and encoder are in chain with common avalon signals for interconnections  

Thanks fo any suggestions.....