LVDS tristating usage

[Altera_Forum]

Hello, 

1. Could anybody suggest whether ALT_OUTBUF_TRI_DIFF can be used at the moment?  I was trying to select Cyclone III, Stratix IV - and it looks like this primitive does not supported at all now. Am I right?   2. I want to tri-state an LVDS bus, more exactly one input line - RX- of my bus. Is it possible for Cyclone III?  What I did, I connected my RX line to the TRI primitive and set the RX line as LVDS in the PIn Planner. Quartus II finished compilation successfully. Does it mean that LVDS input tristating will work for Cyclone III?   Thank you for help! U.

[Altera_Forum]

I don't see a purpose of tri-stating an input. Also, did you consult the bidirectional LVDS application note?

[Altera_Forum]

1. So is this a problem of slaves to tri-state the line? 

 I don't need to have RX biderectional - only a possibility to tri-state it.   2. I was reading "High-Speed Differential Interfaces in Cyclone III Devices" document and "designing with low-level primitives" but did not find something proper.  I need only to know if it is possible to tri-state LVDS in Cyclone III. I've heard different opinions - somebody say that it is not possible for all Altera devices, and somebody told me that it not possible for Cyclone II or some older families only. 

[Altera_Forum]

--- Quote Start ---  I don't need to have RX biderectional - only a possibility to tri-state it.  --- Quote End ---  But why? Tristating only makes sense for an output or a bidirectional pin...

[Altera_Forum]

--- Quote Start ---  but did not find something proper  --- Quote End ---  ???  The said application note instructs you to build a bus LVDS with Cyclone III. Your problem may be different, but you didn't clarify in which regard. As said twice now, tristating a receiver seems meaningless.  If you are possibly referring to dynamical switched termination resistors, they are not provided with Cyclone III. And they won't be useful with bus LVDS anyway, because it's based on a end terminated party line.

[Altera_Forum]

Yes,  

I agree that there is no sence to tri-state inputs.    But what about output pins tri-stating?    I have multiply slaves and It is necessary to avoid signal contention on the slave output (looks like SPI multi-slave environment). So I need to use tri-state buffers and my bus is LVDS bus.  When I connected the slave output line to the tri-state buffer and selected the LVDS standatrd for it I got the following error:   Error: The differential I/O standard LVDS cannot be used on the pin Slave_O, because the specified pin uses a tri-stated output buffer.   Does it mean that it is not possible to tri-state LVDS in all Altera devices? What can be a workaround for this problem?

[Altera_Forum]

The LVDS-tristate driver uses pseudo differential IO, as discussed in detail in the said application note. The respective IO standard with Cyclone III is bus lvds rather than lvds.

[Altera_Forum]

FvM, 

 Thank you very much. Using Bus LVDS was the answer. I was so concentrated on LVDS, so overlooked BLVDS information from the handbooks.   I've created a scheme as in the attachment, the Fitter had no objections. Let's see how it will work. Thank you again.

[Altera_Forum]

I have a similar problem, and get the same answer - allthough I do not even use tristated outputs but delay buffers. 

 I tried to assign BLVDS but do not find it in the assignment editor.:confused:   What do I have to do in detail?

[Altera_Forum]

I wasn't aware of the differences between Cyclone III and Stratix III BLVD implemantation. The most recent Version of AN522 is telling how to:  

  --- Quote Start ---  In Stratix III and Stratix IV devices, BLVDS interface can be implemented using 2.5-V Differential SSTL Class I or II, depending on the current strength requirement.  --- Quote End ---