Quartus TCL vs Quartus GUI

[Altera_Forum]

Hi 

 I have created and compiled a project using the TCL scripting. I now want to use the Quartus GUI to view the build via chip planner etc. In loading the project ing Quartus it requires me to recompile the project before I can view the results in chip planner. The green ticks are not in the task window, therefore it seems that the GUI doesnt pick up the results from the scripting   This doesnt seem right. Is this expected?? We do batch compiles, and I dont want to have to recompile everytime I want to use one of the GUI features

[Altera_Forum]

This is not expected. Once you compile with Quartus (using any method), you should be able to load the resulting database with the Chip Planner. 

I recommend you confirm that you are not accidentally using two different versions of Quartus (e.g. 8.1 to compile, abd 9.0 for the GUI). Also confirm that your scripts are not deleting anything. Maybe you can post your script. You can also try with a new small design. The following three flows should be identical: 1.- From the GUI, click "play" button 2.- From command-line, type "quartus_sh --flow compile <name>" and then open Quartus and see report 3.- From tcl (I am typing from memory, so I may have the exact syntax wrong):  load_package flow  project_open <name>  execute_flow -compile  project_close Then open GUI and open report

[Altera_Forum]

Hi Davka 

 My TCL script is pretty simple. Obviously there is a QPF and QSF etc behind it, which is then what I load into Quartus.   In re-compiling in Quartus I see that there is a few more files created in the \db\ folder. A DDB, a RDB, a CDB.... I'm defintely using the same version, there are no errors in the reports of both operations... Maybe I'm missing something in my TCL??     TCL:   project_open example_case1 load_package flow  execute_module -tool map    set seed "1" # PAR execute_module -tool fit -args "--seed=$seed" # assembler - gen prog file execute_module -tool asm# timing execute_module -tool tan -args "--post_map --zero_ic_delay"  project_close

[Altera_Forum]

--- Quote Start ---  Hi Davka   My TCL script is pretty simple. Obviously there is a QPF and QSF etc behind it, which is then what I load into Quartus.   In re-compiling in Quartus I see that there is a few more files created in the \db\ folder. A DDB, a RDB, a CDB.... I'm defintely using the same version, there are no errors in the reports of both operations... Maybe I'm missing something in my TCL??     TCL:   project_open example_case1 load_package flow  execute_module -tool map    set seed "1"  # PAR execute_module -tool fit -args "--seed=$seed"  # assembler - gen prog file execute_module -tool asm # timing execute_module -tool tan -args "--post_map --zero_ic_delay"  project_close  --- Quote End ---    Hi,  I have your tcl-script with a small design tested. All works fine !  How did you start the tcl-script ? Maybe you can post your project here.  Kind regards  GPK

[Altera_Forum]

Hi  

 I have a BAT file which just does this:   quartus_sh -t build_project.tcl   pause   --------- The QSF file contains the following (have removed the source code lines)   set_global_assignment -name FAMILY "Stratix II" set_global_assignment -name DEVICE EP2S15F484C3 set_global_assignment -name TOP_LEVEL_ENTITY example_top_general_purpose_counter_adl set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2" set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:56:08 AUGUST 12, 2009" set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2" set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON set_global_assignment -name ENABLE_CLOCK_LATENCY ON set_global_assignment -name VHDL_FILE xxxx   The QPF doesnt contain anything of interest:   QUARTUS_VERSION = "9.0" DATE = "17:56:08 August 12, 2009"# Revisions PROJECT_REVISION = "example_counter_case1"   Thanks

[Altera_Forum]

And just to clarify that I'm trying to use Chip Planner in the GUI after running the project via the script. The script itself completes without a problem, but as previously stated the GUI doesnt pickup that the results are up to date :confused:

[Altera_Forum]

--- Quote Start ---  Hi    I have a BAT file which just does this:   quartus_sh -t build_project.tcl   pause   --------- The QSF file contains the following (have removed the source code lines)   set_global_assignment -name FAMILY "Stratix II" set_global_assignment -name DEVICE EP2S15F484C3 set_global_assignment -name TOP_LEVEL_ENTITY example_top_general_purpose_counter_adl set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2" set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:56:08 AUGUST 12, 2009" set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2" set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON set_global_assignment -name ENABLE_CLOCK_LATENCY ON set_global_assignment -name VHDL_FILE xxxx   The QPF doesnt contain anything of interest:   QUARTUS_VERSION = "9.0" DATE = "17:56:08 August 12, 2009" # Revisions PROJECT_REVISION = "example_counter_case1"   Thanks  --- Quote End ---    Hi,  strange, I did the same in my testcase and all works fine. Is the build_project.tcl identical to the script you posted begore ? Can you post a Quartus project as testcase here ? Otherwise I don`t know how I can help.  Kind regard  GPK