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As I've looked at Part V of the Lab Exercise 1,it looks very complicated,so i wanted to make sure my codes for 7 segment display are in order and easy to read.is this so?
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY chiong3 IS PORT( SW :IN STD_LOGIC_VECTOR (1 DOWNTO 0); HEX0 :OUT STD_LOGIC_VECTOR (0 TO 6); LEDR :OUT STD_LOGIC_VECTOR (1 DOWNTO 0)); end chiong3; architecture Behavior of chiong3 is SIGNAL NUM :STD_LOGIC_VECTOR (1 DOWNTO 0); SIGNAL FLOP:STD_LOGIC_VECTOR (0 To 6); begin NUM(1) <= SW(1); NUM(0) <= SW(0); LEDR(0) <= SW(0); LEDR(1) <= SW(1); FLOP <="1000010" WHEN NUM = "00" ELSE "0110000" WHEN NUM = "01" ELSE "1001111" WHEN NUM = "10" ELSE "1111111"; HEX0 <= FLOP; END Behavior;Link Copied
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Manage to create a simpler version which will fit Part 5 of Lab1 Examples.
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY chiong3_1 IS PORT( s :IN STD_LOGIC_VECTOR (1 DOWNTO 0); Display :OUT STD_LOGIC_VECTOR (0 TO 6); red :OUT STD_LOGIC_VECTOR (1 DOWNTO 0)); end chiong3_1; architecture Behavior of chiong3_1 is begin red<=S; Display <="1000010" WHEN s = "00" ELSE "0110000" WHEN s = "01" ELSE "1001111" WHEN s = "10" ELSE "1111111"; END Behavior;
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