Stratix II GX transceivers and REFCLK input clock

[Altera_Forum]

Hi, 

 In a design involving a Stratix II GX 30 we are looking at the possibility to input one reference clock to the transceivers. Therefore, the reference clock input pin of one quad will need to be forwarded to the other quad via the inter quad signals (possibly). Is the inter quad link automatically used by Quartus and nothing needs to be explicitly instantiated or is it necessary to specify something in the code ? Is it common place to use these inter quad links to provide one clock reference to several quads ?  Best regards,  JF

[Altera_Forum]

You shoudn't have any problems, and don't have to do anything special besides assigning the pins. 

For transceiver designs, I strongly recommend not designing by datasheet. Be sure to make a shell design with transceivers, the correct pinouts, pin location and standard assignments etc. and make sure it compiles before going to board layout. Quartus catches issues much better than trying to figure it out from the datasheet. Also, this isn't wasted work, since that shell will be used in the real design. It's far too easy to make a mistake and not know about it without this check.

[Altera_Forum]

Quartus will automatically determine that the refclk needs to be picked up from the inter-quad route. It will also automatically configure the mux to the PLL to use the appropriate refclk input. I concur with Rysc on doing test compiles beforehand. 

 Jake

[Altera_Forum]

Hi, 

 Thank you for the information. To ensure the design is working and that the right routing resources are used then a post routing simulation or a board would be the way to ensure it works to go further than compile process not flagging an error. Is it not possible to see the kind of routing used with the chip editor ? I have tried to use the chip editor but was not very successful at seeing the routing resources used. Moreover, is there any behavior difference to expect between the clock directly availbale to a transceiver and one provided via the interquad bus (jitter performance mainly) ?  Best regards,  JF  Best regards,  JF Hasson

[Altera_Forum]

Your latter question is a good one? And I don't believe Altera releases jitter characterization for the various clock routing paths. 

 Therefore, I can only speak from experience. I do have a single using 16 transceiver channels. I have 4 reference clocks (each as an input to 4 seperate quads) and those 4 reference clocks are made available to all other quads (see the attached PDF). The output data rate on each transceiver is about ~3Gbps max.   I do not see noticeable differences in jitter performance between the transceiver outputs. However, what we did observe is that the various reference clocks to interfere with each other.  So if I shut down reference clocks 2 and 3, the overall transmitter output jitter improves. Basically the more reference clocks I enable the more the jitter increases. (And we've shown it's not on the board but in the FPGA). However, in my case, I believe it is primarily due to the relationship in frequencies of the reference clocks.  Jake