USB 2.0 core problem

Altera_Forum · ‎08-12-2009

Hi all,

I am having some troubles with the USB2.0HR core from SLS corp.

I am using the USB2.0HR version 2.2 on Quartus II 8.1.

I successfully created the NIOS II sopc and loaded into the Cyclone III. I opened the example program portinterface in the NIOS II IDE. I compiled it and loaded that into the FPGA. I can see the "USB open successfully" message showing up. However, when I connect the board to the PC. The PC says the "USB Device is not recognized". And the VID and PID are 0x0000 as shown in the device manager.

I am sure the signal lines are connected correctly between the FPGA and the Phy device. And I can see the 60MHz Phy clock coming out. So what else could go wrong?

thanks

Altera_Forum · ‎09-02-2009

Do you face the same problem with the reference design provided in the package? Did you create your own SOPC system?

Regards,

Nazia

Altera_Forum · ‎03-30-2010

I actually have a question for you instead of an answer :), I have Cyclone III which has a USB connector that is used as you know to upload SOF, debug, etc. With the SLS core are you using the same "connector"? or do you have another external USB connector attached?

As I am a beginner I was wondering how my final design would look like, I mean when I move it from the starter kit to an actual hardware as a product, would I just use a USB connector and the core will do the job, or do I still need other things to connect to? Finally (sorry) how much that USB core cost? or is it free in the SOPC?

Thanks in advance for your help.

Altera_Forum · ‎05-11-2010

I use quartus9.0. In this software there is a usb2.0hr ip core produced by SLS compony.I want to know whether the usb2.0hr ip core need to be registered when I use it or it maybe an open core.