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Does PLL VCCA require isolation if PLL isn't used?

Altera_Forum
Honored Contributor II
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Hi Folks, 

 

I'm currently designing a board with an EP1C3T100 that doesn't use the PLL. When checking the Cyclone manual for board layout best practice it recommends isolating VCCA. I quote - 

 

"Even if the PLL is not used, the VCCA power must be connected to a 1.5-V supply. The power connected to VCCA must be isolated from the power to the rest of the Cyclone FPGA, or any other digital device on the board. The following sections describe three different methods for isolating VCCA". 

 

If the PLL isn't used is it acceptable to just tie this to 1.5V supply without the isolation? 

 

Thanks in advance, 

 

DH 

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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

If the PLL isn't used is it acceptable to just tie this to 1.5V supply without the isolation? 

 

--- Quote End ---  

 

It`s not good. 

Look at manual, there are 3 way to solve this task: 

1. Separate VCCA Power Plane 

2. Partitioned VCCA Island within VCCINT Plane 

3. Thick VCCA Traces - I think it will good choice for you (The traces should be at least 20 mils thick, 3 capacitor, ferrite bead; loot at manual). 

P.S: I saw some (cycloneI) board which were working without the isolation. You will able to risk if you want. IMHO 3 way it`s easy.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Even if the PLL is not used, the VCCA power must be connected to a 1.5-V supply. The power connected to VCCA must be isolated from the power to the rest of the Cyclone FPGA. 

--- Quote End ---  

In my opinion, the second clause doesn't refer to the first. Standard VCCINT bypass should be sufficient in this case. 

 

As an additional remark, if you intended to use the PLL though: VCCA isolation mainly means separate bypass caps and a filter (R or ferrite) to VCCINT. If you place the caps (I have typically 1n + 100n) directly between VCCA and GNDA, there's no particular purpose of 1. a separate plane, 2. a VCCA island, 3. thick traces.
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Altera_Forum
Honored Contributor II
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The purpose for isolating the power to the PLL is to minimize jitter on the PLL's clock outputs. If you're not using the PLL, no need to reduce the jitter. Still, I'd at least follow FvM's guidelines and add proper bypass. 

 

Jake
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Altera_Forum
Honored Contributor II
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Thanks for all your responses, especially FvM & jakobjones. I've gone with FvM's suggestion...Many thanks for your time.

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